Semi-Negated Data Coding Reduces Bit Switching Activity
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Solution Overview
Problem
Existing data coding methods, such as twos-complement, result in extensive bit transitions during sign changes, leading to increased power consumption in digital signal processing systems, and alternative methods like modulus and sign representation introduce additional coding complexities and restricted ranges.
Innovation Solution
A modified data coding method using a semi-negated representation, where bits n-2 to 0 are negated if the n-1 bit is zero, reducing bit switches during transitions and maintaining compatibility with existing processing architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional twos-complement representation is used, then algebraic operations on signed numbers are easily performed and arithmetic-logic unit design is simplified, but extensive bit transitions occur during sign changes leading to increased power consumption
Solution Approach 1:
The patent segments the data representation into two parts: a sign bit (n-1) that indicates the sign, and a magnitude part (bits n-2 to 0) that represents the absolute value. This segmentation allows the magnitude bits to remain unchanged during sign transitions, reducing bit switching activity and power consumption while maintaining compatibility with existing arithmetic-logic units that operate on twos-complement data
Solution Approach 2:
The patent changes the parameter representation from traditional twos-complement to a modified format where the magnitude is stored in a different encoding (using the n least significant bits to represent the magnitude directly). This parameter change reduces the number of bit transitions during sign changes from approximately n bits to just 1 bit (the sign bit), thereby reducing power consumption
2Use of energy by moving object
If modulus and sign representation is adopted to reduce switching activity, then power consumption is reduced, but additional coding for zero is introduced and representation range is restricted
Solution Approach 1:
The patent makes the n least significant bits serve dual purposes: they represent the magnitude of the number while also enabling the representation of both positive and negative values through the sign bit. This multi-functionality eliminates the need for separate coding of zero and maintains the full representation range of twos-complement, avoiding the drawbacks of modulus and sign representation
3Ease of operation
If bits are extensively switched during sign transitions in twos-complement, then algebraic operations are simplified, but power consumption increases
Solution Approach 1:
The patent segments the data into sign bit and magnitude bits, allowing independent handling of sign changes without affecting magnitude representation. This segmentation enables sign transitions to involve only 1 bit change instead of multiple bit changes, reducing energy loss during transitions while preserving the simplicity of algebraic operations
Solution Approach 2:
The patent introduces an intermediary representation format that acts as a bridge between the arithmetic-logic unit's native twos-complement operation and the reduced-power representation. The coding/decoding circuit serves as an intermediary that converts data to and from this low-power format, allowing the ALU to continue using simple twos-complement operations while the external representation consumes less power
Data Source
AI summary
The method of coding data within a data processing unit includes a representation as twos-complement and a coded representation of the data. The coded representation is a semi-negated representation. A data processing unit includes a memory device connected bidirectionally to a data bus, itself connected to a processing architecture which includes at least one arithmetic-logic unit. Advantageously, the data processing unit includes at least one data coding/decoding block connected between the processing architecture and the data bus.