Semiconductor Active Pattern Width Optimization
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Solution Overview
Problem
Current semiconductor devices face challenges in optimizing the arrangement and dimensions of active patterns and power rails to enhance electric characteristics, such as efficiency and integration density, while maintaining compatibility with existing manufacturing processes.
Innovation Solution
The semiconductor device incorporates a specific arrangement of active patterns and power rails on a substrate, where certain active patterns have widths that are at least two times those of adjacent patterns, with specific overlapping and non-overlapping configurations to improve electric characteristics, and includes gate-all-around type transistors for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of active patterns is increased to improve electric characteristics, then the device area and integration density are adversely affected
Solution Approach 1:
The patent applies different width specifications to different active patterns based on their functional requirements. Specifically, the second active pattern has a width of at least two times the first active pattern width, while the third active pattern has a width of at least two times the fourth active pattern width. This local differentiation optimizes electric characteristics in critical regions without uniformly increasing device area.
Solution Approach 2:
The patent introduces asymmetric width relationships among active patterns and power rails. The second active pattern is wider than the first, and the third active pattern is wider than the fourth, creating an asymmetric layout that optimizes current distribution and electric characteristics while maintaining compact overall device dimensions.
2Reliability
If active patterns are arranged with specific overlapping configurations to improve electric characteristics, then the manufacturing complexity increases
Solution Approach 1:
The patent segments the device into distinct regions with first and second active patterns in a first region, and third and fourth active patterns in a second region. This segmentation allows for systematic arrangement where power rails can be positioned to overlap with specific active patterns, simplifying the manufacturing process while achieving the desired electric characteristics.
Solution Approach 2:
The patent utilizes vertical overlapping in the cross-sectional dimension to achieve functional optimization. Power rails are positioned to vertically overlap with specific active patterns (second and third patterns) while avoiding others (first and fourth patterns), creating a three-dimensional arrangement that improves electric characteristics without increasing planar complexity.
3Reliability
If the width ratio between active patterns is optimized for performance, then the compatibility with existing manufacturing processes is reduced
Solution Approach 1:
The patent specifies precise width parameter relationships (second active pattern width ≥ 2 × first active pattern width, third active pattern width ≥ 2 × fourth active pattern width) that can be implemented through standard photolithography scaling. These parameter changes maintain compatibility with existing manufacturing processes while achieving the desired performance optimization through controlled dimensional variations.
Data Source
AI summary
A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.