Semiconductor Active Region Protrusion for Buried Wiring Uniformity
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Solution Overview
Problem
In semiconductor devices, the variation in active region width due to side etching during trench formation leads to inconsistent gate electrode film thickness and wiring resistance, affecting the performance of DRAMs.
Innovation Solution
The semiconductor device design includes a memory cell region with a first isolation region and a second active region that protrudes from the insulating film, with a constant width in the second active region to maintain uniformity and reduce wiring resistance variations by ensuring consistent film thickness of buried word lines and buried wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of active region is reduced to increase transistor density, then the number of transistors per unit area increases, but the side etching reaches the central portion of the active region causing height variation and film thickness inconsistency
Solution Approach 1:
The patent applies local quality by forming a protruding portion in the active region at the boundary with the peripheral region. This local structural modification ensures that the active region width at the boundary is larger than in the internal region, preventing side etching from reaching the central portion while maintaining high transistor density in the internal area. The protruding portion creates a localized width increase that compensates for the overall reduced active region width.
Solution Approach 2:
The patent implements preliminary action by pre-forming the protruding portion in the active region before the side etching process. This advance structural preparation ensures that when side etching occurs, the etching front does not reach the central portion of the active region, thereby preventing height variation and film thickness inconsistency before they can occur.
2Adaptability or versatility
If the active region width varies from minimum value Y5 to maximum value Y6, then the layout flexibility increases, but the wiring resistance variation increases due to inconsistent gate electrode film thickness
Solution Approach 1:
The patent maintains layout flexibility through the crank-shaped boundary design while applying local quality by forming a protruding portion at the boundary region. This localized width increase ensures that the active region width at the boundary is sufficient to prevent side etching penetration, thereby ensuring uniform gate electrode film thickness and consistent wiring resistance, while other regions can maintain varied widths for layout optimization.
3Ease of manufacture
If the side etching progresses further due to decreased active region width, then the trench formation completeness improves, but the active region height decreases causing film thickness variation
Solution Approach 1:
The patent applies preliminary action by pre-forming the protruding portion in the active region before the side etching process. This advance structural preparation ensures that when side etching occurs, the etching front encounters the protruding portion first and does not reach the central portion of the active region, thereby preventing excessive etching and height reduction while still achieving complete trench formation in the intended areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the variation in wiring resistance and enhances the performance of buried word lines and transistors by maintaining a constant width of the active regions, thereby improving the reliability and efficiency of the semiconductor device.
Implementation Method 1
an insulating film located in the first and second isolation regions
Implementation Method 2
a second active region divided off by the first and second isolation regions and protruding from an upper surface of an insulating film
Implementation Method 3
maintain uniformity and reduce wiring resistance variations by ensuring consistent film thickness of buried word lines and buried wiring
Data Source
AI summary
Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant.