Semiconductor Channel Structure With Air Gap for Leakage Suppression
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in achieving high integration density, particularly in reducing leakage currents and improving electrical properties due to the miniaturization of planar metal oxide semiconductor FETs, which traditional semiconductor devices struggle to address effectively.
Innovation Solution
A semiconductor device design featuring a lower structure with a first insulating layer, an air gap, and a second semiconductor layer with a different conductivity type, which reduces leakage currents by preventing junction leakage and punch-through phenomena, thereby enhancing electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar metal oxide semiconductor FETs are miniaturized to achieve high integration density, then integration density is improved, but leakage currents increase and electrical properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET channel structures with vertical fins extending from the substrate. This dimensional change increases the effective channel width and integration density while maintaining better electrical control and reduced leakage currents through the vertical field effect transistor architecture
Solution Approach 2:
The patent employs composite material structures including metal oxide semiconductor channels combined with high-k dielectric gate insulators and metal gate electrodes. This composite approach enables high integration density while maintaining superior electrical properties and reduced leakage through the complementary characteristics of each material layer
2Productivity
If patterns are reduced to fine width and spacing to achieve high integration density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The FinFET structure utilizes vertical fin dimensions to achieve high integration density without requiring proportionally smaller lateral pattern dimensions. The vertical extension of fins provides additional scaling dimension that reduces the burden on lateral lithography resolution and pattern fabrication precision
3Reliability
If operational properties are improved through device redesign, then electrical properties are improved, but device complexity increases
Solution Approach 1:
The device is segmented into distinct functional layers including substrate, FinFET channel structures, gate electrodes, dielectric layers, and metal interconnect layers. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall electrical performance and managing structural complexity through modular design
Data Source
AI summary
A semiconductor device includes; a gate structure intersecting an active region, and a plurality of channel layers, extending on the substrate in a second direction, and surrounding the plurality of channel layers; a source/drain region contacting the plurality of channel layers on at least one side of the gate structure and including a first semiconductor material with first impurities having a first conductivity type; and a lower structure in contact with the active region and below the source/drain region. The lower structure includes a first layer disposed on the active region and including an insulating material; a second layer disposed on the first layer and including a second semiconductor material; with an air gap defined by the first layer and the second layer, wherein the second semiconductor material of the second layer has no conductivity type or has a second conductivity type different from the first conductivity type.