Semiconductor Memory Device Air Gaps Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the increased parasitic capacitance between conductive structures due to narrower distances deteriorates their performance, and existing methods to lower parasitic capacitance by reducing the dielectric constant of dielectric materials are limited.
Innovation Solution
The semiconductor device incorporates line-type air gaps formed between bit line structures and conductive plugs, achieved through a method involving the formation of a multi-layer spacer with a sacrificial spacer, which is removed to create air gaps, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between conductive structures is reduced to increase integration, then device integration is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful dielectric material between the bit line and contact plugs, replacing it with air gaps. This removal of the dielectric material eliminates the source of parasitic capacitance while maintaining the narrow spacing required for high integration, directly resolving the contradiction between integration and parasitic capacitance.
Solution Approach 2:
The patent changes the dielectric parameter from a solid dielectric material (with finite dielectric constant) to air (with dielectric constant approximately equal to 1). This parameter change dramatically reduces the parasitic capacitance between conductive structures while allowing them to remain closely spaced for high integration.
2Object-generated harmful factors
If dielectric material with lower dielectric constant is used to reduce parasitic capacitance, then parasitic capacitance is decreased, but there is a limit to how much it can be reduced
Solution Approach 1:
The patent achieves the maximum possible reduction in dielectric constant by replacing solid dielectric material with air gaps. Since air has a dielectric constant of approximately 1 (the lowest practical value), this eliminates the limitation inherent in using progressively lower dielectric constant materials, allowing parasitic capacitance to be reduced to the minimum possible level.
3Object-generated harmful factors
If air gaps are formed between bit line and contact plugs, then parasitic capacitance is decreased, but additional fabrication steps are required
Solution Approach 1:
The patent performs preliminary actions by forming the multi-layer spacer structure and sacrificial spacer before finalizing the contact plug formation. The sacrificial spacer is intentionally left in place during intermediate steps and then removed in a controlled manner to create the air gaps, allowing the complex structure to be built systematically and then finalized with minimal additional steps.
Solution Approach 2:
The patent uses a sacrificial spacer as an intermediary element that facilitates the creation of air gaps. The sacrificial spacer is temporarily introduced during fabrication, guides the formation of the multi-layer spacer structure, and is then removed to leave the desired air gap configuration. This intermediary approach simplifies the overall process compared to attempting to directly pattern and etch air gaps.
Data Source
AI summary
A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.