Air Gaps and Low-k Layers in Semiconductor Nanowire Fabrication
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Solution Overview
Problem
In the manufacturing of semiconductor devices, particularly FinFETs and GAA FETs, controlling lateral etching during nanowire release is challenging, leading to issues with gate-to-source/drain capacitance and reduced circuit speed due to insufficient etching control and the absence of an etch stop layer, which affects the precision of nanowire formation and device performance.
Innovation Solution
The introduction of one or more low-k layers and/or air gaps between the gate electrode and the source/drain epitaxial layer to reduce capacitance and improve etching control, with the use of insulating layers such as silicon nitride and low-k dielectric materials to create inner spacers that isolate the gate from the source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used without an etch stop layer, then nanowire release can be achieved, but lateral etching control is insufficient leading to poor manufacturing precision
Solution Approach 1:
An etch stop layer is formed preliminarily before the nanowire release etching process. This pre-formed layer serves as a controlled barrier that limits lateral etching, ensuring precise nanowire release without compromising manufacturing precision or excessively increasing process complexity
Solution Approach 2:
The etch stop layer acts as an intermediary element between the etching process and the nanowire structure. It mediates the etching action by providing a controlled stopping point, thereby improving lateral etching control and manufacturing precision without requiring complete process redesign
2Productivity
If gate electrode is placed close to source/drain region, then device density is improved, but gate-to-source/drain capacitance increases reducing circuit speed
Solution Approach 1:
Low-k layers and air gaps are introduced as intermediary elements between the gate electrode and source/drain region. These intermediaries reduce parasitic capacitance while maintaining the close proximity needed for high device density, thereby preserving circuit speed without sacrificing productivity
Solution Approach 2:
Low-k dielectric materials with porous structures are used to fill spaces between gate and source/drain. The porous nature provides lower dielectric constant, reducing capacitance effects and improving circuit speed while allowing compact layout for high device density
3Reliability
If FinFET gate structure surrounds fin on three surfaces, then gate control is improved, but bottom part of channel is far from gate electrode reducing control effectiveness
Solution Approach 1:
The gate structure transitions from three-sided wrapping in FinFET to complete surrounding in GAA FET by adding vertical dimension control. The gate electrode extends to surround the channel from all sides including the bottom, achieving full depletion and improved control effectiveness through three-dimensional geometry
Solution Approach 2:
High-k dielectric materials are used in the gate structure to enhance the electric field strength and improve gate control over the channel. This allows effective control even in three-dimensional configurations where gate-to-channel distance varies, maintaining reliability and control effectiveness
4Reliability
If GAA FET is used to surround all side surfaces of channel, then short-channel effects are reduced, but manufacturing complexity increases at sub 10-15 nm nodes
Solution Approach 1:
Sacrificial layers are formed preliminarily to define the channel structure before gate wrapping is implemented. This preliminary structuring simplifies the subsequent gate formation process, enabling GAA FET manufacturing at sub 10-15 nm nodes without excessive complexity while maintaining short-channel effect control
Solution Approach 2:
The channel structure is segmented into discrete sections with sacrificial layers between them, allowing independent processing and assembly. This segmentation simplifies the manufacturing of complex GAA structures by breaking down the process into manageable steps, reducing overall manufacturing complexity while preserving device reliability
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.