Semiconductor Air Void Isolation for Switch Device Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor structures face challenges with capacitance disturbance and reduced switching speed as devices miniaturize, due to residual capacitance.
Innovation Solution
A semiconductor structure with a multi-layer stack having filling layers of different etching rates, including a first and second filling layer with distinct etching rates, and an air void surrounded by dielectric material, is embedded in a semiconductor substrate with a switch device positioned over the air void to enhance isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor structure with silicon on insulator (SOI) is used to increase isolation effect, then the parasitic capacitance effect is reduced and switching speed is increased, but as devices become smaller, residual capacitance causes capacitance disturbance and reduced switching speed
Solution Approach 1:
The semiconductor structure is divided into multiple isolation regions including deep trench isolation portions extending to the substrate and shallow trench isolation portions extending to the epitaxial layer, creating segmented isolation zones that progressively reduce capacitance disturbance at different depths and locations
Solution Approach 2:
The isolation structure is extended into the vertical dimension by forming deep trench isolation portions that reach the substrate and combining them with shallow trench isolation portions, creating a three-dimensional isolation architecture that enhances isolation effect beyond conventional planar approaches
2Reliability
If the multi-layer stack with different filling layers is formed, then the air void can be properly formed to improve isolation, but the manufacturing process becomes more complex
Solution Approach 1:
Different filling layers with distinct etching rates are used in specific locations within the multi-layer stack, allowing selective removal of certain layers to form air voids at precise positions while maintaining other structures, thereby achieving localized isolation enhancement without uniformly increasing complexity throughout the entire device
Solution Approach 2:
The different etching rates of the filling layers enable self-selective removal during the manufacturing process, where the etch process automatically removes the intended layer to form air voids without requiring additional complex patterning or masking steps, allowing the structure to self-organize the isolation features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air void provides improved isolation, reducing capacitance disturbance and increasing switching speed, while the multiple etching rates facilitate proper air void formation.
Implementation Method 1
the capacitance remaining in the semiconductor device may result in capacitance disturbance and reduced switching speed
Data Source
AI summary
The present disclosure provides a method for manufacturing a semiconductor structure having different filling layers. The method includes forming a multi-layer stack in a semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second layer, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias. The method further includes recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device.


