Semiconductor Alignment Key With Dummy Holes For 3D Stack Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device manufacturing, the increasing number of stacks in three-dimensional devices leads to alignment accuracy errors due to offsetting of laser beams used for alignment signals, resulting in weakened signal measurement.
Innovation Solution
The formation of alignment keys with dummy holes and channel insulation layers on a semiconductor substrate, where critical dimension values differ, generating a step during etching that can be utilized as an alignment signal, reducing alignment errors by varying the etching quantity and forming capping layers with distinct heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of stacks in three-dimensional devices is increased, then device functionality and integration are improved, but alignment accuracy deteriorates due to laser beam offsetting and signal weakening
Solution Approach 1:
The alignment key structure is segmented into multiple components: dummy holes with different critical dimensions, channel insulation layers, and capping layers with different heights. This segmentation creates distinct reflection surfaces that help maintain accurate alignment signals even in three-dimensional devices with multiple stacks
Solution Approach 2:
Different regions of the alignment key are given different local qualities through varying critical dimensions of dummy holes and different capping layer heights. This creates localized reflection characteristics that enhance signal detection accuracy without compromising overall device functionality
2Measurement precision
If dummy holes with different critical dimension values are formed, then a measurable step is generated for alignment detection, but device complexity increases
Solution Approach 1:
The alignment key structure with dummy holes of different critical dimensions serves multiple functions: it generates measurable steps for alignment detection, provides reference markers for lithography alignment, and maintains compatibility with existing manufacturing processes. This multi-functionality reduces the need for separate alignment structures
Solution Approach 2:
The invention transitions from two-dimensional alignment markers to three-dimensional structures with varying heights and critical dimensions. The vertical dimension is utilized through different capping layer heights and channel insulation layer configurations, creating measurable steps that enhance alignment signal detection in the vertical dimension
Data Source
AI summary
An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.