Semiconductor Alignment Key Layout for Dense 3D Cell Stacks
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Solution Overview
Problem
As semiconductor devices become highly integrated and smaller in size, the space for alignment keys in the edge region decreases, making it challenging to secure sufficient space for cell alignment keys, which can lead to manufacturing defects and reduced yield.
Innovation Solution
The semiconductor device design includes peripheral alignment keys in the device region, allowing sufficient space for cell alignment keys in the edge region, with these keys being disposed on the planarization insulating layer and having different widths and surface roughness compared to peripheral alignment keys, ensuring secure placement without overlapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are made highly integrated and smaller in size, then device density and integration level are improved, but the space for alignment keys in the edge region decreases
Solution Approach 1:
The patent moves alignment keys from the traditional edge region to the device region, utilizing the vertical stacking dimension. Cell alignment keys are positioned on upper insulating layers above the substrate level, while peripheral alignment keys are placed in the device region at different vertical levels, effectively using three-dimensional space to resolve the two-dimensional space constraint.
Solution Approach 2:
The alignment key system is divided into two distinct types: peripheral alignment keys in the device region and cell alignment keys in the edge region. This segmentation allows each type to be optimized for its specific function and location, with peripheral keys having smaller dimensions suitable for the device region and cell keys having larger dimensions for reliable alignment in the edge region.
2Reliability
If cell alignment keys are placed in the edge region, then alignment function is provided, but sufficient space cannot be secured due to device size reduction
Solution Approach 1:
Cell alignment keys are positioned on upper insulating layers (e.g., fourth insulating layer) above the substrate level, utilizing the vertical dimension to provide sufficient space for alignment keys without occupying additional horizontal area in the constrained edge region.
Solution Approach 2:
Different regions are assigned different alignment key types with different dimensions: peripheral alignment keys with smaller dimensions (width of 1-3 μm) are placed in the device region where space is limited, while cell alignment keys with larger dimensions (width of 3-5 μm) are placed in the edge region where slightly more space is available, optimizing the alignment function for each region's specific constraints.
3Reliability
If peripheral alignment keys are used in the device region, then alignment reference is provided, but space for cell alignment keys is reduced
Solution Approach 1:
The alignment key system is segmented into peripheral alignment keys for providing alignment reference in the device region, and separate cell alignment keys for ensuring sufficient alignment space in the edge region. This segmentation allows both functions to coexist without competing for the same limited space.
Solution Approach 2:
Peripheral alignment keys are placed in the device region at the substrate level or lower, while cell alignment keys are positioned on upper insulating layers in the edge region, utilizing vertical separation to provide both alignment reference and sufficient alignment space without spatial conflict.
Data Source
AI summary
A semiconductor device includes a first peripheral circuit structure and a cell stack structure disposed on the first peripheral circuit structure and including electrode layers and inter-electrode insulating layers that are alternately and repeatedly stacked, the first peripheral circuit structure includes a first substrate, first peripheral transistors disposed on the first substrate, a first peripheral insulating layer covering the first substrate and the first peripheral transistors, and a first peripheral alignment key on the first peripheral insulating layer, and the first peripheral alignment key overlaps the cell stack structure.