Semiconductor Analytic Fields for Defect Positioning
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Solution Overview
Problem
Current failure analysis methods for semiconductor devices are inefficient in accurately identifying and locating defects in the back-end process, leading to prolonged development times and potential damage to test wafers due to the lack of precise information about defect positions.
Innovation Solution
A structured approach involving analytic fields with arrayed semiconductor transistors, wordlines, and bitline structures with varying metal patterns and plugs, allowing for the determination of defect types and positions through electrical testing and focused ion beam analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wafer-cutting processes are performed without defect position information, then defects may be enlarged for SEM inspection, but a large number of cutting processes are required and test wafers are damaged
Solution Approach 1:
The patent applies preliminary action by forming analytic fields with specific test patterns (contact chains, vias, metal patterns) before the back-end manufacturing process. These pre-configured test structures enable direct identification of defect positions and types without requiring multiple trial wafer-cutting operations, thus reducing development time while maintaining measurement precision.
2Measurement precision
If multiple wafer-cutting processes are performed to locate defects, then defect positions can be found, but test wafers are damaged to such degree that failure analysis becomes impossible
Solution Approach 1:
The patent forms analytic fields containing test patterns (contact chains, vias, metal patterns of different layers) before the back-end process. These pre-configured test structures allow direct identification of defect positions and types through electrical testing, eliminating the need for multiple destructive wafer-cutting operations and preserving the test wafer for continued analysis.
Solution Approach 2:
The patent creates analytic fields that are separate test structures (copies) containing the same interconnection elements as the actual device but dedicated to failure analysis. These analytic fields serve as surrogate test targets, allowing defect identification without damaging the primary device under test.
3Reliability
If conventional test patterns are used, then interconnection defects can be found, but detailed information about defect types and positions cannot be obtained
Solution Approach 1:
The patent segments the test pattern into multiple analytic fields, each containing specific test structures (contact chains, vias, metal patterns of different layers). Each segment is designed to test specific interconnection elements, allowing detailed identification of defect types and precise location information that conventional unified test patterns cannot provide.
Solution Approach 2:
The patent applies local quality by creating different types of test structures (contact chains with specific resistance values, vias with specific dimensions, metal patterns of different layer configurations) in different regions of the analytic field. Each local structure is optimized to reveal specific defect characteristics, enabling detailed information about defect types and positions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables quick and accurate identification of defects in semiconductor devices, reducing development time and minimizing wafer damage by precisely locating and analyzing defects within the semiconductor substrate.
Implementation Method 1
semiconductor substrates at the defect positions may be precisely cut out by means of a focused ion beam (FIB)
Data Source
AI summary
In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.