Semiconductor Antenna Structures for Monitoring Plasma-Induced Damage
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Solution Overview
Problem
Existing methods for protecting semiconductor transistors from plasma process-induced damages (PIDs) are inadequate, particularly in advanced technology nodes where plasma etching processes can cause gate dielectric breakdown and transistor failure due to charge accumulation.
Innovation Solution
Implementing a first and second antenna structure with different etching rates, where the first antenna is exposed to plasma earlier than the second, providing a discharge path for charges and reducing gate-source voltage, and monitoring PIDs by forming larger vias over the second antenna to evaluate transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma etching processes are used in BEOL processes, then manufacturing precision and productivity are improved, but plasma process-induced damages occur causing gate dielectric breakdown and transistor failure
Solution Approach 1:
A shielding plate structure is introduced as an intermediary element between the plasma environment and the transistor gate. The shielding plate, positioned adjacent to the gate and electrically connected to a power source, acts as a mediator that controls the plasma interaction with the gate dielectric, preventing direct harmful plasma exposure while allowing the etching process to continue
Solution Approach 2:
The shielding plate is configured to generate an electric field or plasma barrier in advance before the harmful plasma reaches the gate dielectric. By applying voltage to the shielding plate prior to or during plasma exposure, a protective environment is created that prevents charge accumulation and dielectric breakdown before they can occur
2Reliability
If shielding structures are added to protect transistors from PIDs, then transistor reliability is improved, but device complexity increases
Solution Approach 1:
The shielding plate serves multiple functions simultaneously: it acts as a physical barrier against plasma, an electrical shield through its power connection, and a controllable element that can be activated or deactivated based on process requirements. This multi-functionality reduces the need for additional separate protection structures
Solution Approach 2:
The shielding plate is positioned locally adjacent to the gate structure, providing protection only where it is most needed (at the gate dielectric interface). This localized approach avoids the complexity of comprehensive shielding across the entire device while maintaining reliability at critical points
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the susceptibility of transistors to plasma-induced damages by decreasing gate-source cross voltage, thereby protecting the transistor and allowing for reliable evaluation of PIDs without additional protection devices.
Implementation Method 1
a first antenna coupled to a gate structure of the transistor... providing a discharge path for charges and reducing gate-source voltage
Implementation Method 2
performing a plasma etching process to the dielectric layer, thereby forming first trenches exposing the first metal line and second trenches exposing the second metal line
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, a method includes forming a first antenna coupled to a gate structure of a transistor, the first antenna comprising a first metal line, forming a second antenna coupled to a source/drain feature of the transistor, the second antenna comprising a second metal line, wherein the first metal line and the second metal line are disposed within a same metallization layer, forming a dielectric layer over the metallization layer, performing a plasma etching process to the dielectric layer, thereby forming first trenches exposing the first metal line and second trenches exposing the second metal line, respectively, wherein the first trenches and second trenches are formed in a chronological order, and forming first and second conductive vias in the first trenches and second trenches, respectively.