Semiconductor Array Testing Circuit Signal Timing
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Solution Overview
Problem
Conventional testing apparatuses for semiconductor device arrays face issues with signal delays in transmission lines, leading to potential test errors due to unequal co-existing periods of clock and data signals, which can be affected by external interference.
Innovation Solution
A testing apparatus with separate circuits for transmitting clock, input command, and data signals to rows and selecting signals to columns, ensuring equal differences in arrival times between devices within the same row, thereby synchronizing signal periods and reducing test errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the input command signal and data signal are transmitted in parallel in the device array, then the testing apparatus can operate efficiently, but the arrival times of the signals become unequal at different devices, causing test errors
Solution Approach 1:
The patent divides the signal transmission into two independent parts: row signals (clock, input command, data) transmitted through row lines, and column signals (selecting signal) transmitted through column lines. This segmentation allows each signal type to be optimized for its specific transmission path, ensuring equal arrival times at all devices within the same row while maintaining efficient parallel operation across the entire array.
2Manufacturing precision
If the co-existing period of clock signal and data signal is extended to ensure successful data writing, then writing accuracy is improved, but the testing time is increased
Solution Approach 1:
The patent applies preliminary action by transmitting the clock signal, input command signal, and data signal simultaneously through the row lines to all devices before the selecting signal is transmitted through the column lines. This preliminary transmission ensures that all necessary signals are already in place at each device, eliminating the need for extended co-existing periods and reducing overall testing time while maintaining writing accuracy.
3Measurement precision
If separate transmission paths are used for row and column signals, then signal timing is improved, but the device complexity increases
Solution Approach 1:
The patent implements universality by designing the row lines to carry multiple signals (clock, input command, data) simultaneously, and the column lines to carry the selecting signal. This multi-functional approach allows the testing apparatus to achieve precise signal timing through separate transmission paths while avoiding the need for additional complex timing control mechanisms, thus improving measurement precision without proportionally increasing device complexity.
Data Source
AI summary
A testing apparatus and a method for testing a semiconductor devices array, which includes a plurality of rows and a plurality of columns, are provided. The testing apparatus includes a first testing circuit and a second testing circuit. The first testing circuit connects and transmits a clock signal, an input command signal and a data signal to at least one of the rows of the semiconductor devices array. The second testing circuit connects and transmits a selecting signal to at least one of the columns of the semiconductor devices array. Between two devices in a row, a difference in arrival times of the clock signal, a difference in arrival times of the input command signal, and a difference in arrival times of the data signal are equal.