Semiconductor Array Contour Layout for Uniform Metal Plating
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Solution Overview
Problem
Semiconductor devices face variations in metal portion heights due to electric field concentration and manufacturing errors, leading to defects and performance issues.
Innovation Solution
A semiconductor device design featuring a polygonal contour shape with interior angles greater than 90° on the semiconductor substrate, where a virtual quadrilateral circumscribing the array portion does not overlap its vertices, and a manufacturing method involving resist application, pattern formation, and electroplating to form metal portions with controlled heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional rectangular array portion design is used, then manufacturing process is simple, but electric field concentration occurs at vertices causing height variations in metal portions
Solution Approach 1:
The array portion contour shape is designed to be asymmetric with respect to the virtual quadrilateral vertices, specifically ensuring that the contour does not overlap or approach within a predetermined distance (e.g., 1/10 to 1/5 of the minimum side length) of any vertex. This asymmetric positioning prevents electric field concentration at the vertices, thereby eliminating the root cause of height variations in the metal portions while maintaining manufacturing simplicity.
Solution Approach 2:
The invention applies local quality by specifically modifying the contour shape characteristics in the regions near the virtual quadrilateral vertices, while keeping other portions of the array portion design conventional. The contour is designed to maintain appropriate spacing from vertices locally, which prevents electric field concentration at these critical locations without requiring complete redesign of the entire array structure.
2Productivity
If electroplating is used to form metal portions, then manufacturing efficiency is high, but height variations occur due to electric field distribution differences
Solution Approach 1:
The invention changes the geometric parameters of the array portion contour shape, specifically the distances from the contour to the virtual quadrilateral vertices. By ensuring these distances are within a predetermined range (not less than 1/10 and not more than 1/5 of the minimum side length of the virtual quadrilateral), the electric field distribution during electroplating is optimized, resulting in uniform current density and consistent metal portion heights while maintaining high manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents electric field concentration and height variations, reducing defects and ensuring consistent performance by limiting height variations to 10% or less.
Implementation Method 1
applying a resist on a semiconductor substrate; forming a pattern having a shape corresponding to the plurality of metal portions in the resist
Implementation Method 2
forming a plurality of first conductive portions on the semiconductor substrate by forming a metal layer in openings of the patterned resist
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate and an array portion. The array portion includes a plurality of metal portions arranged on the semiconductor substrate. When a virtual quadrilateral circumscribing minimally a contour shape of the array portion on the semiconductor substrate is set, the contour shape of the array portion does not overlap each of four vertices of the virtual quadrilateral.