Semiconductor Device Asymmetric Diffusion Layer Junction Breakdown Voltage
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Solution Overview
Problem
As semiconductor devices, such as NAND nonvolatile memory devices, face challenges in reducing the chip surface area while maintaining high reliability, particularly due to decreased junction breakdown voltage and increased contact resistance as the pitch of bit lines and transistors is reduced, leading to deteriorated reliability.
Innovation Solution
The semiconductor device configuration includes a first and second circuit unit with interconnects and transistors, where the transistors have specific diffusion layers and gate electrodes arranged to reduce the chip surface area while maintaining high junction breakdown voltage, with the use of an intermediate unit for voltage control and isolation, allowing for a zigzag or staggered configuration of connection regions to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pitch of bit lines and transistors is reduced to reduce chip surface area, then the occupied surface area is reduced, but the junction breakdown voltage decreases and reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating asymmetric diffusion layer configurations where specific connection regions (first and second connection regions) have different width characteristics. The first connection region maintains a larger width to ensure adequate junction breakdown voltage, while other regions can be more compact, allowing localized optimization of reliability without compromising overall chip area reduction goals
Solution Approach 2:
The patent employs asymmetry by configuring the first connection region with a width in the second direction that is greater than the width of the second connection region. This asymmetric design allows the critical connection region to maintain larger dimensions for reliable electrical connection and high breakdown voltage, while other regions can be minimized for area efficiency
2Area of stationary object
If the pitch of bit lines and transistors is reduced to reduce chip surface area, then the occupied surface area is reduced, but the contact resistance increases and reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating asymmetric diffusion layer configurations where specific connection regions (first and second connection regions) have different width characteristics. The first connection region maintains a larger width to ensure adequate junction breakdown voltage, while other regions can be more compact, allowing localized optimization of reliability without compromising overall chip area reduction goals
Solution Approach 2:
The patent employs asymmetry by configuring the first connection region with a width in the second direction that is greater than the width of the second connection region. This asymmetric design allows the critical connection region to maintain larger dimensions for reliable electrical connection and high breakdown voltage, while other regions can be minimized for area efficiency
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first circuit unit having first and second interconnects, a second circuit unit having third and fourth interconnects, and an intermediate unit provided therebetween and having first and second transistors juxtaposed to each other along a direction perpendicular to a direction from the first circuit unit toward the second circuit unit. A high impurity concentration region in a first connection region of one diffusion layer of the first transistor is connected to the first interconnect, and other diffusion layer is connected to the third interconnect. A distance from the first connection region to a gate is longer than a distance from the second connection region to a gate. An midpoint region with a narrower width than the first connection region is provided between the gate and the first connection region of the one diffusion layer of the first transistor.