Semiconductor Package Asymmetric Pad Stacking
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Solution Overview
Problem
Semiconductor devices with fine pitches face contact failure due to misalignment during stacking, and existing methods using micro-bumps are limited in shortening signal transmission paths for high-speed connections.
Innovation Solution
A semiconductor package structure with a semiconductor stack comprising a first lower chip, a second lower chip, a gap filler, and an upper chip, where the upper surface pads of the lower chips are larger than the lower surface pads of the upper chip, allowing direct bonding and reducing contact failure by utilizing the gap filler as an additional pad region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If micro-bumps are used for connection, then high-speed connection is achieved, but the signal transmission path cannot be sufficiently shortened
Solution Approach 1:
The patent transitions from lateral connection to vertical stacking, changing the spatial dimension of connection. By stacking chips vertically with direct pad-to-pad bonding, the signal transmission path is dramatically shortened compared to lateral micro-bump connections, while achieving high-speed connection through direct electrical contact between adjacent chip layers.
Solution Approach 2:
The patent eliminates the micro-bump intermediate connection structure by implementing direct pad-to-pad bonding between stacked chips. This removes the micro-bump layer and its associated signal path length, achieving shorter transmission paths while maintaining high-speed connection capability through direct electrical contact.
2Productivity
If fine pitch is used for high integration, then device integration is improved, but contact failure occurs due to misalignment during stacking
Solution Approach 1:
The patent designs the lower chip pads with larger area than the upper chip pads, creating a deliberate size asymmetry that acts as a tolerance buffer. This 'cushioning' design allows for misalignment during stacking while ensuring that the upper pad remains within the bonding area of the lower pad, preventing contact failure and maintaining reliable electrical connection despite positioning variations.
Solution Approach 2:
The patent employs asymmetric pad sizing where the lower chip pads have a larger area than the upper chip pads. This asymmetric configuration creates a tolerance zone that accommodates misalignment during the stacking process, ensuring that even with positioning errors, the upper pad remains adequately supported by the larger lower pad area, thereby maintaining contact reliability.
Data Source
AI summary
Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.