Semiconductor Back Grinding Contamination Prevention
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Solution Overview
Problem
The existing methods for reducing the thickness of semiconductor devices through back grinding face challenges such as contamination of the principal surface due to foreign materials penetrating through the grinding fluid and dicing failures caused by abrasive grains adhering to the dicing blade, especially as the planar dimensions of semiconductor chips become smaller, leading to increased dicing blade damage and reduced manufacturing efficiency.
Innovation Solution
A manufacturing method involving the lamination of multiple insulating layers and a metal pattern in the scribe regions, with a guard ring and insulating layers to prevent fluid penetration and reduce the load on the dicing blade, including the formation of trenches and stoppers to enhance the sealing effect and prevent contamination and dicing failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the back surface of the semiconductor wafer is ground to reduce thickness, then the thickness of the semiconductor chip is reduced, but foreign materials penetrate through the grinding fluid into the principal surface causing contamination
Solution Approach 1:
A protective sheet is introduced as an intermediary barrier between the grinding fluid and the principal surface of the semiconductor wafer. The protective sheet prevents foreign materials generated during back grinding from penetrating through the grinding fluid and contaminating the integrated circuits on the principal surface, while still allowing the thickness reduction to be achieved.
Solution Approach 2:
The protective sheet is applied to the principal surface before the back grinding process begins. This preliminary protective action prevents the harmful penetration of foreign materials into the device region during subsequent grinding operations, countering the contamination risk before it occurs.
2Object-affected harmful factors
If polyimide resin banks are formed in scribe regions to prevent grinding fluid penetration, then contamination is prevented, but the low hardness of polyimide causes abrasive grains to adhere to the dicing blade reducing manufacturing efficiency
Solution Approach 1:
The invention changes the material parameter of the bank structure from soft polyimide resin to hard metal material. This parameter change maintains the sealing function to prevent grinding fluid penetration while eliminating the problem of abrasive grain adhesion during dicing, thereby preserving manufacturing efficiency.
Solution Approach 2:
The invention uses a composite structure where a metal bank is formed in the scribe region. The metal material provides both the sealing function to prevent fluid penetration and the hardness to resist abrasive grain adhesion, combining multiple desirable properties in a single material solution.
3Area of stationary object
If the planar dimension of semiconductor chips is reduced to make devices smaller, then device size is reduced, but the number of dicing lines increases leading to more dicing blade damage
Solution Approach 1:
Metal banks are formed in the scribe regions before the dicing process. These pre-formed metal structures reinforce the scribe lines and provide support during dicing operations, preventing dicing blade damage even when the number of dicing lines increases due to smaller chip dimensions.
Solution Approach 2:
The scribe regions are segmented into discrete metal bank structures positioned at critical locations. This segmentation provides localized reinforcement where it is most needed during dicing, allowing the blade to cut through smaller chips with reduced damage risk.
Data Source
AI summary
A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.