Semiconductor Barrier Layer Impurity Distribution for Latch-up Strength

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In trench-type insulated gate bipolar transistors (IGBTs), the barrier layer hinders hole passage, leading to increased loss and decreased latch-up strength during turn-off due to submerged resistance.

Innovation Solution

The semiconductor device incorporates barrier layers with specific impurity concentration distributions and arrangements to facilitate hole passage, reducing submerged resistance and enhancing latch-up strength by optimizing the structure and positioning of barrier layers relative to emitter and contact layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a barrier layer is formed below emitter layers and contact layers to improve carrier injection enhancement effect, then carrier injection enhancement is improved, but holes cannot easily pass through the barrier layer causing increased loss and decreased latch-up strength

Engineering Contradiction:
Improvelatch-up strengthVSAvoidturn-off loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by creating different impurity concentration regions within the barrier layer. The barrier layer has higher impurity concentration directly beneath the emitter layers to enhance carrier injection, while having lower impurity concentration in regions between trenches to facilitate hole passage. This spatial variation in impurity concentration allows simultaneous optimization of both carrier injection enhancement and hole transport properties.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the impurity concentration parameter within the barrier layer to resolve the contradiction. By adjusting the impurity concentration distribution - higher concentration for carrier injection enhancement and lower concentration for hole passage - the patent optimizes both latch-up strength and turn-off loss characteristics without requiring structural modifications to the barrier layer's fundamental configuration.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If barrier layer is formed to improve carrier injection enhancement effect, then carrier injection enhancement is improved, but submerged resistance increases when holes pass through the barrier layer

Engineering Contradiction:
Improvelatch-up strengthVSAvoidsubmerged resistance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating different impurity concentration regions within the barrier layer. The barrier layer has higher impurity concentration directly beneath the emitter layers to enhance carrier injection, while having lower impurity concentration in regions between trenches to facilitate hole passage. This spatial variation in impurity concentration allows simultaneous optimization of both carrier injection enhancement and hole transport properties.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the impurity concentration parameter within the barrier layer to resolve the contradiction. By adjusting the impurity concentration distribution - higher concentration for carrier injection enhancement and lower concentration for hole passage - the patent optimizes both latch-up strength and turn-off loss characteristics without requiring structural modifications to the barrier layer's fundamental configuration.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9318588B2Semiconductor device
Publication Date: 2016.04.19 KK TOSHIBA
  • US9318588B2 patent drawing
  • US9318588B2 patent drawing
  • US9318588B2 patent drawing

AI summary

In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.