Semiconductor Package Barrier Metal Layer Adhesion

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current semiconductor packages face challenges with reduced adhesive force between insulating layers and redistribution conductive patterns, leading to increased thermal stress and potential peeling, which shortens the package's lifetime and increases failure rates.

Innovation Solution

The method involves forming a barrier metal layer along the sidewalls of openings in the insulating layers and redistribution conductive patterns, which enhances the adhesive force and reduces thermal stress by creating a heterojunction with different thermal expansion coefficients, thereby increasing the package's lifetime and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If insulating layers and redistribution conductive patterns are directly bonded without a barrier metal layer, then the manufacturing process is simpler, but the adhesive force is insufficient and thermal stress causes peeling

Engineering Contradiction:

Improveadhesive forceVSAvoidstructure complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The patent introduces a barrier metal layer as an intermediate material between the insulating layer and redistribution conductive pattern. This creates a composite structure where the barrier metal layer combines the adhesive properties needed for bonding with thermal expansion characteristics that reduce stress, thereby improving overall joint strength without excessive complexity

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The barrier metal layer serves as an intermediary element between the insulating layer and redistribution conductive pattern. It mediates the thermal expansion mismatch between these two materials and provides a bonding interface that enhances adhesive force, preventing direct contact and potential peeling

Inventive Principle:

Principle #24Intermediary (Mediator)

2Duration of action of stationary object

If a barrier metal layer is added to reduce thermal stress and increase adhesive force, then the package lifetime is extended, but the manufacturing process becomes more complex

Engineering Contradiction:

Improvepackage lifetimeVSAvoidmanufacturing ease

Core Design Contradiction:

Duration of action of stationary objectVSEase of manufacture

Solution Approach 1:

The patent modifies the thermal expansion parameters of the bonding interface by introducing a barrier metal layer with intermediate thermal expansion properties. This parameter change reduces thermal stress accumulation during temperature cycling, thereby extending package lifetime while the added manufacturing step remains manageable

Inventive Principle:

Principle #35Parameter changes

3Stress or pressure

If the barrier metal layer is formed to create heterojunction with different thermal expansion coefficients, then thermal stress is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:

Improvethermal stressVSAvoidforming precision

Core Design Contradiction:

Stress or pressureVSManufacturing precision

Solution Approach 1:

The barrier metal layer is selectively formed only in specific regions where thermal stress and bonding are critical - namely at the interfaces between insulating layers and redistribution conductive patterns. This localized application reduces overall thermal stress without requiring high precision across the entire structure, maintaining manufacturing feasibility

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively increases the adhesive force between insulating layers and redistribution conductive patterns, reducing thermal stress and peeling, resulting in a longer-lasting and more reliable semiconductor package with reduced failure rates.

Implementation Method 1

creating a heterojunction with different thermal expansion coefficients, thereby increasing the package's lifetime and reliability

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11018108B2Method of fabricating semiconductor package

Publication Date: 2021.05.25 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.