Semiconductor Package Barriers for Underfill Keep-In Zones

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Solution Overview

Problem

Existing semiconductor devices face challenges in containing underfill and adhesive materials within narrow boundaries due to the need for larger keep-out-zones (KOZs), which occupy valuable space and hinder functionality enhancement.

Innovation Solution

The implementation of barriers formed by walls using small molecules, oligomers, polymers, or inorganic materials, applied through jetting or extrusion techniques, to create a keep-in-zone (KIZ) that confines these materials within a smaller area, allowing for increased functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional KOZ methods are used to prevent material leakage, then material containment is achieved, but valuable substrate space is occupied and functionality is hindered

Engineering Contradiction:
Improvematerial containmentVSAvoidsubstrate space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The barrier structure is segmented into multiple functional layers including a base layer, a barrier layer with vertical walls, and an overfill layer. This segmentation allows each layer to perform its specific function efficiently, containing materials within a smaller footprint while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar KOZ containment to three-dimensional barrier structures with vertical walls. By adding the vertical dimension, materials are confined within a smaller horizontal area while the barrier extends vertically to prevent leakage, thus resolving the space occupation issue.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If barrier structures are implemented to contain materials, then material leakage is prevented, but manufacturing complexity increases

Engineering Contradiction:
Improveleakage preventionVSAvoidbarrier structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The barrier layer's properties are adjusted by controlling the deposition process parameters such as thickness, material composition, and deposition rate. These parameter changes enable the barrier to achieve effective containment while maintaining manufacturability through standard deposition techniques.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The barrier structure uses composite material layers including the base layer, barrier layer, and overfill layer, each with specific material properties. This composite approach allows optimization of each layer for its specific function while maintaining overall structural integrity and manufacturability.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20250364474A1Barriers in seminconductor devices
Publication Date: 2025.11.27 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20250364474A1 patent drawing
  • US20250364474A1 patent drawing
  • US20250364474A1 patent drawing

AI summary

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including one or more barriers to form a keep-out-zone or a keep-in-zone. In various embodiments, system include a substrate including a first layer, a wall coupled to a first surface of the first layer, and a material coupled to the first surface of the first layer. The wall can be configured to block the material from flowing or expanding outside of the wall.