Semiconductor Conductive Patterns With Bent Step Portions
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Solution Overview
Problem
The formation of staircase-shaped pad regions in vertical memory devices becomes increasingly difficult as the vertical distance between stacked memory cells decreases, making it challenging to prevent electrical short circuits between conductive patterns.
Innovation Solution
A semiconductor device design featuring conductive patterns with extension and step portions, where the step portions have bent upper and lower surfaces, increasing the vertical distance between neighboring patterns and reducing the likelihood of electrical short circuits, is implemented. The conductive patterns and insulation patterns are alternately stacked, with the step portions being integral to the pad structure, allowing for a staircase shape that enhances spacing and reduces short circuit risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical distance between stacked memory cells is reduced, then the density of vertical memory devices is improved, but the formation of staircase-shaped pad regions becomes increasingly difficult and electrical short circuits between conductive patterns occur more frequently
Solution Approach 1:
The conductive patterns are designed with bent upper and lower surfaces at step portions, transitioning from flat two-dimensional planes to three-dimensional curved surfaces. This dimensional change allows the pad regions to maintain proper spacing and electrical isolation even when the overall vertical distance between memory cells is reduced, thereby enabling high density while preserving manufacturing precision
Solution Approach 2:
The step portions of the conductive patterns incorporate curved surfaces instead of sharp edges or flat surfaces. The bent upper and lower surfaces at the steps create a smooth transition that prevents electrical short circuits while maintaining the staircase shape, allowing reliable pad region formation at reduced vertical distances
2Quantity of substance
If the vertical distance between stacked memory cells is reduced, then the density of vertical memory devices is improved, but the probability of electrical short circuits between neighboring conductive patterns increases
Solution Approach 1:
By introducing vertical curvature to the conductive pattern surfaces through bent upper and lower surfaces at step portions, the design adds a dimensional buffer that maintains electrical isolation. This three-dimensional configuration prevents direct contact between neighboring conductive patterns even when vertical spacing is minimized, thereby preventing short circuits while achieving high density
Solution Approach 2:
The bent surfaces at the step portions create a built-in protective configuration that anticipates and prevents electrical short circuits. The curved geometry provides a natural clearance buffer before contact could occur, cushioning against the reduced vertical distance and ensuring reliable electrical isolation between conductive patterns
Data Source
AI summary
A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.