Semiconductor Device Block Separator for Memory Stack Division
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Solution Overview
Problem
As the height of semiconductor memory block stacks increases, there is a need for a stable division method to improve the integration of memory cells with three-dimensional arrangements, as existing technologies face challenges in maintaining stability and efficiency in the division and manufacturing process.
Innovation Solution
A semiconductor device with a block separator comprising a semiconductor film and a multi-layered insulating film, which surrounds the semiconductor film, and memory block stacks divided by the block separator, each including interlayer insulating films and conductive patterns alternately stacked, with channel structures passing through and electrically coupled to the memory cells, is manufactured using a process involving the formation of vertical stacks, protection patterns, and channel holes to create spaces for filling the block separator and channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of memory block stacks is increased to improve integration of memory cells, then the integration density is improved, but the stability of division for memory block stacks deteriorates
Solution Approach 1:
The patent divides the memory block stack into multiple segments by introducing block separators at different heights. These separators partition the tall stack into manageable sections, maintaining stability while preserving the high integration density achieved through increased stack height. The segmentation allows each section to be independently supported and divided without compromising the entire structure.
Solution Approach 2:
The block separator acts as an intermediary element between adjacent memory block stacks. It provides a stable dividing structure that mediates the interaction between tall stacks, enabling reliable division and isolation of memory blocks while maintaining the overall high-density three-dimensional arrangement.
2Quantity of substance
If the number of alternating vertical interlayer insulating films and conductive patterns is increased to improve integration, then the integration density is improved, but the manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming protection patterns, creating block slits, forming channel holes, and filling operations. This segmentation of the manufacturing process into manageable steps reduces complexity by allowing each step to be optimized independently while building toward the high-density final structure.
Solution Approach 2:
Protection patterns are formed preliminarily before the main stack formation and division processes. These pre-formed patterns serve as templates and guides for subsequent manufacturing steps, simplifying the overall process by establishing the structural framework in advance rather than attempting to create the complex multi-layer structure in a single operation.
3Manufacturing precision
If block separators and channel structures are formed separately to ensure precision, then the manufacturing precision is improved, but the manufacturing time increases
Solution Approach 1:
The formation of block separators and channel structures is merged into a single simultaneous filling operation. By combining these two formation processes into one step, the patent achieves both manufacturing precision (through coordinated formation) and time efficiency (by eliminating sequential processing delays), resolving the contradiction between precision and speed.
Solution Approach 2:
The filling process for block separators and channel structures is performed continuously in a single operation rather than as separate discrete steps. This continuous action maintains precision through consistent process conditions while reducing total manufacturing time by eliminating interruptions and setup changes between operations.
Data Source
AI summary
The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.