Semiconductor Boundary Scan Test Circuit Area Optimization
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Solution Overview
Problem
The existing boundary scan test circuits for semiconductor memory systems occupy a large area within the memory chip, making it difficult to perform direct tests on the memory after packaging, as they require a test circuit and test pad for signal verification between the processor and memory.
Innovation Solution
A semiconductor apparatus with a receiver, signal processing unit, multiplexer (MUX) unit, latch unit, and clock selection unit that allows for the selection and processing of input signals, enabling a boundary scan test by switching between normal and test modes to optimize space usage and facilitate testing without occupying excessive memory area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a boundary scan test circuit is inserted into the memory to verify signal input path between processor and memory, then test capability is improved, but chip area is increased
Solution Approach 1:
The test circuit is merged with the memory structure by utilizing existing memory cells and circuit elements to form the boundary scan functionality. The memory cells are configured to serve dual purposes: normal memory operation and test signal routing, eliminating the need for separate dedicated test circuit area.
Solution Approach 2:
The memory cells and associated circuits are designed to perform multiple functions: normal data storage and retrieval operations, and boundary scan test operations. The same physical structures are reused for both operational modes through control signals that reconfigure the circuit behavior.
2Ease of operation
If a test circuit is inserted into the memory to enable post-packaging testing, then test accessibility is improved, but device complexity is increased
Solution Approach 1:
The memory structure itself provides the test functionality without requiring external test equipment to access internal signals. The boundary scan circuit uses the memory's own pads and internal structures to route test signals, making the memory self-testing capable and simplifying the overall test system architecture.
3Ease of operation
If extensive test pads are used for boundary scan testing, then test signal routing is improved, but chip area is increased
Solution Approach 1:
The test signal routing utilizes the existing vertical and horizontal signal paths within the memory structure rather than adding new dedicated test pad rows. The boundary scan functionality leverages the multi-dimensional signal distribution network already present in the memory array for efficient signal routing without additional area.
Data Source
AI summary
A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal.