Semiconductor Bridge Epitaxy for RF Parasitic Reduction
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Solution Overview
Problem
The challenge in forming semiconductor devices with multiple structures in a wide gate pitch region is the pattern loading effect, which leads to non-uniformity in semiconductor structures due to differences in growth rates, affecting the performance of RF FET devices by increasing parasitic capacitance and signal loss.
Innovation Solution
The method involves forming semiconductor devices with a wide gate pitch by creating recessed regions between gate structures and using epitaxy to grow semiconductor structures and bridges, ensuring uniformity and reducing parasitic capacitance through strategic surface plane management and epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor material is grown simultaneously in regions of higher pattern density and lower pattern density, then the manufacturing process is simplified, but the growth rates differ causing non-uniformity in semiconductor structure thickness
Solution Approach 1:
The patent introduces dummy structures in low-pattern-density regions to create locally uniform pattern density across the substrate. This ensures that semiconductor material grows at consistent rates in both high and low density regions, achieving uniform thickness while maintaining the simplicity of simultaneous growth processing.
Solution Approach 2:
The dummy structures are formed beforehand in the low-pattern-density regions before the semiconductor material growth step. This preliminary action equalizes the pattern density distribution, ensuring uniform growth conditions are established prior to the actual semiconductor material deposition.
2Area of stationary object
If contact structures are positioned closer to gate structures, then device area is reduced, but parasitic capacitance increases degrading RF performance
Solution Approach 1:
The gate pitch region is segmented into multiple discrete gate structures with controlled spacing. By dividing the gate array into segments with optimized pitch distances, the patent achieves a balance between minimizing device area and maintaining sufficient spacing to reduce parasitic capacitance between contact structures and gate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with reduced parasitic capacitance and resistance, enabling higher switching speed and lower RF signal losses, particularly beneficial for high-frequency RF applications.
Implementation Method 1
A first epitaxy process is performed to fill the first recessed region to form a first semiconductor structure and fill the second recessed region to form a second semiconductor structure. A second epitaxy process is performed to grow a semiconductor bridge over the elevated section.
Data Source
AI summary
A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.