Semiconductor Package Bridge Layout to Reduce Interposer Warpage
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Solution Overview
Problem
Current semiconductor packages using interposers face challenges such as warpage, poor yield, and high manufacturing costs due to thermal expansion mismatches and difficulties in forming fine patterns, especially when using organic interposers.
Innovation Solution
A semiconductor package design featuring a first connection structure with a redistribution layer directly on semiconductor chips, an interconnection bridge surface-mounted to connect chips, and a second connection structure embedding the bridge to reduce layers and enhance yield and processability, while controlling warpage and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an organic interposer is used to connect semiconductor chips, then the device complexity is reduced, but warpage occurs due to thermal expansion mismatch
Solution Approach 1:
The patent extracts the interconnection function from the traditional interposer and implements it through separate interconnection bridges that are surface-mounted on the connection structure. This eliminates the need for a bulky organic interposer while maintaining the electrical connection function, thereby reducing device complexity without causing warpage.
Solution Approach 2:
The connection structure serves multiple functions: it provides mechanical support for the semiconductor chips, enables electrical redistribution through redistribution layers, and facilitates interchip communication through surface-mounted interconnection bridges. This multi-functionality replaces the need for a separate organic interposer, reducing complexity while maintaining stability.
2Reliability
If a silicon-based interposer is used for high-specification connections, then connection reliability is improved, but manufacturing cost increases and fine pattern formation becomes difficult
Solution Approach 1:
The patent segments the interconnection function into two parts: redistribution layers formed on the connection structure and interconnection bridges surface-mounted to connect chips. This segmentation allows the use of simpler, more cost-effective materials and processes compared to traditional silicon interposers, while maintaining connection reliability through the distributed connection architecture.
Solution Approach 2:
The patent employs cost-effective materials and simpler manufacturing processes for the connection structure and interconnection bridges, replacing expensive silicon interposers. The design prioritizes ease of manufacture and cost-effectiveness while achieving the required connection reliability through the alternative architectural approach.
3Reliability
If multiple layers are used to connect chips, then connection reliability is improved, but manufacturing complexity and yield issues increase
Solution Approach 1:
The patent transitions from a vertical multi-layer stacking approach to a hybrid approach where interconnection bridges are surface-mounted on the connection structure. This dimensional change allows connections to be established in a more accessible plane, reducing manufacturing complexity and improving yield while maintaining connection reliability through the bridge architecture.
Data Source
AI summary
A semiconductor package includes a first connection structure having first and second surfaces and including a first redistribution layer, a first semiconductor chip disposed on the first surface and having a first connection pad electrically connected to the first redistribution layer, a second semiconductor chip disposed around the first semiconductor chip on the first surface and having a second connection pad electrically connected to the first redistribution layer, an interconnection bridge disposed on the second surface to be spaced apart from the second surface and connected to the first redistribution layer through a connection member to electrically connect the first and second connection pads to each other, and a second connection structure disposed on the second surface to embed the interconnection bridge and including a second redistribution layer electrically connected to the first redistribution layer.