Semiconductor Buffer Structure for Chip Stress Absorption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor device packages are prone to damage due to stress-induced cracks in chips during manufacturing, primarily caused by the fragile nature of chip structures and process-related flaws, leading to limited yield and quality issues.
Innovation Solution
A semiconductor device package is designed with a buffer structure that controls the gap between the chip and substrate, using a vesicant material to absorb impact and prevent direct contact between the bridge chip and substrate, thereby providing mechanical support and facilitating proximity communication between active chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are directly mounted on the substrate without buffer structure, then the device structure is simple and manufacturing is easy, but the chips are susceptible to stress-induced cracks and damage during manufacturing
Solution Approach 1:
The patent introduces a buffer structure as an intermediary element between the chip and the substrate. This buffer structure includes a buffer layer and a cavity that absorbs stress and prevents direct transmission of mechanical stress from the substrate to the chip, thereby reducing chip damage while maintaining a manageable package structure.
Solution Approach 2:
The buffer structure is designed to provide beforehand cushioning by creating a cavity and buffer layer that absorb impact and stress before they can reach the chip. This preventive measure protects the chip from stress-induced cracks during the manufacturing process and beyond.
2Productivity
If the chip structure is made more fragile to achieve higher integration, then the functionality and density improve, but the susceptibility to manufacturing damage increases
Solution Approach 1:
The buffer structure serves as a protective intermediary that decouples the chip from direct mechanical stress. This allows the chip to be designed with higher integration and more fragile structures while the buffer absorbs the mechanical stress, thereby improving manufacturing yield without compromising structural strength.
3Manufacturing precision
If gap control between chip and substrate is not implemented, then the manufacturing process is simpler, but stress distribution is poor leading to more cracks
Solution Approach 1:
The buffer layer acts as an intermediary that precisely controls the gap between the chip and substrate. This buffer layer can be designed with specific thickness and material properties to achieve the desired gap control, improving stress distribution and manufacturing precision while keeping the process manageable.
4Reliability
If the buffer structure is made more substantial to better absorb impact, then chip protection improves, but the device size and complexity increase
Solution Approach 1:
The buffer structure is designed with local quality by concentrating the buffer material in specific regions where stress and impact are most likely to occur. The cavity and buffer layer are strategically positioned to provide maximum protection with minimal volume, improving impact absorption capability without significantly increasing package size.
Solution Approach 2:
The buffer structure utilizes porous or cavitated materials that provide high impact absorption capability per unit volume. The cavity within the buffer structure allows for efficient stress absorption while maintaining a compact overall package volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer structure effectively reduces chip damage, enhances yield, and improves product quality by absorbing mechanical impact and maintaining chip stability during manufacturing, ensuring reliable interconnections and signal communication.
Implementation Method 1
forming a vesicant material on a substrate or on the backside surface of the bridge chip; expanding the vesicant material by heating the substrate to form a buffer structure filling a gap between the substrate and the bridge chip
Implementation Method 2
expanding the vesicant material by heating the substrate to form a buffer structure filling a gap between the substrate and the bridge chip
Data Source
AI summary
A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.