Semiconductor Buffer Control for Request Overtaking

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Solution Overview

Problem

In first-in, first-out (FIFO) buffer control systems, when a request written earlier is hindered from transmission, it prevents subsequent requests from being read until the earlier request is processed, leading to increased waiting times and decreased processing capacity in destination buffers with available space.

Innovation Solution

A semiconductor device with a buffer system that includes a first buffer for storing requests and a second buffer for storing identification information, allowing the entry selector to identify and read requests from the first buffer based on destination availability, enabling requests to be read from the first buffer even if the preceding request's destination is full, by using entry number management and arbitration units to manage and prioritize requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If FIFO buffer control method is used, then the configuration is simple and implementation is easy, but processing capacity decreases when earlier requests cannot be transmitted

Engineering Contradiction:
Improvebuffer control configurationVSAvoidprocessing capacity
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the buffer control into multiple destination-specific control structures (destination buffers and destination entry number buffers) rather than a single FIFO queue. This allows independent management of requests for different destinations, enabling selective processing without being blocked by requests to other destinations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic request selection based on destination buffer availability. The entry selector dynamically chooses which request to process next based on real-time destination status, rather than following a fixed FIFO order. This dynamic adaptation maintains high processing capacity while destinations are available.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If FIFO buffer control method is used, then implementation is easy, but waiting time increases for subsequent requests when earlier requests are blocked

Engineering Contradiction:
Improveimplementation easeVSAvoidwaiting time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent performs preliminary organization of requests by destination, storing entry numbers in destination-specific buffers before actual processing. This preliminary segmentation allows the system to quickly identify and access requests for destinations that are currently available, avoiding the time loss of sequentially searching through blocked requests.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces destination entry number buffers as intermediary structures between the main buffer and destination buffers. These intermediaries store and manage request identifiers, enabling efficient matching of requests to available destinations without direct sequential scanning, thus reducing waiting time.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If requests are processed in strict FIFO order, then buffer control is simple, but transmission efficiency decreases when destinations are full

Engineering Contradiction:
Improvebuffer control mechanismVSAvoidtransmission efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent applies different control characteristics to different destinations. Each destination has its own buffer and entry number buffer, allowing localized optimization where requests can be processed as soon as their specific destination is available, rather than waiting for global FIFO order. This local quality differentiation maintains simplicity while improving transmission efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamic request reordering based on destination availability. When a destination becomes available, the corresponding request can be selected and processed immediately, creating a dynamic processing order that adapts to real-time system state rather than maintaining a static FIFO sequence.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11443783B2Semiconductor device
Publication Date: 2022.09.13 FUJITSU LTD
  • US11443783B2 patent drawing
  • US11443783B2 patent drawing
  • US11443783B2 patent drawing

AI summary

A semiconductor device includes a memory device configured to have a first buffer and a second buffer, the first buffer storing a plurality of requests sent to a plurality of destinations, the second buffer storing identification information of the entry associated with a first destination of a first request written to first buffer; and an entry selector configured to identify the first destination from the plurality of destinations when the identification information of the entry is stored in the second buffer, and to read the first request from the plurality of requests stored in the first buffer by using the first destination.