Power Semiconductor Device With Localized Buffer Layer
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Solution Overview
Problem
Current power semiconductor devices face a trade-off between achieving low ON-state voltage and high breaking capability, with existing technologies limiting the improvement of this relationship, particularly in insulated gate bipolar transistors (IGBTs) and other semiconductor devices during turn-off and recovery operations.
Innovation Solution
The design incorporates a semiconductor substrate with a drift region, a collector region only in the active area, and a buffer layer with higher impurity concentration, along with a well region and ballast resistance region to distribute temperature rise and enhance breaking capability without increasing ON-state voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type layer is provided in the extraction region connected to the emitter electrode, then the current breaking capability during turn-off operation is improved, but a local temperature rise occurs at the boundary between the extraction region and termination region
Solution Approach 1:
The patent applies local quality by providing the p-type layer only in specific regions (extraction region and interface area) while maintaining different doping concentrations and structures in different areas. The p-type layer has higher impurity concentration in the extraction region compared to the drift region, creating localized electrical properties that improve current breaking capability without causing uniform temperature rise across the entire device.
Solution Approach 2:
The patent introduces an interface area as an intermediary region between the active area and edge termination area. This interface area contains a p-type layer that acts as a mediator to gradually transition the electrical properties, distributing the current breaking function across multiple regions (extraction region and interface area) rather than concentrating it at one boundary, thereby reducing local temperature rise.
2Reliability
If lattice defects are introduced in the termination region to facilitate carrier annihilation, then the breaking capability during turn-off operation is improved, but the ON-state voltage increases
Solution Approach 1:
The patent applies local quality by introducing p-type doping (which creates lattice defects) only in the termination region and interface area, while keeping the active area and drift region undoped or lightly doped. This localized approach allows carrier annihilation to occur in the termination region without affecting the electrical properties in the active area, thus improving breaking capability while maintaining low ON-state voltage.
Solution Approach 2:
The patent segments the device into distinct functional regions: active area for low-voltage operation, extraction region for current breaking, interface area for transition, and edge termination area for carrier annihilation. By separating these functions into different spatial zones, the patent achieves both low ON-state voltage (in active area) and high breaking capability (in termination region) without compromise.
3Reliability
If the p-type layer is extended into the edge termination area, then the carrier annihilation is enhanced, but the ON-state voltage increases due to the extended depletion region
Solution Approach 1:
The patent applies local quality by providing the p-type layer with higher impurity concentration specifically in the extraction region and interface area, while using lower or zero doping concentration in the edge termination area. This creates localized zones with different electrical properties: the high-doping regions facilitate carrier annihilation, while the low-doping regions maintain low ON-state voltage by minimizing depletion region extension.
Solution Approach 2:
The patent applies partial action by providing the p-type layer in the extraction region and interface area but deliberately limiting or omitting it in the edge termination area. This partial presence of the p-type layer is sufficient to achieve carrier annihilation and current breaking functions without excessive extension into the termination region, thereby avoiding the penalty of increased ON-state voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses local temperature rises, maintaining low ON-state voltage while achieving high breaking capability by distributing temperature and optimizing electrical field strength across the device.
Implementation Method 1
The buffer layer has a portion located between the drift region and the collector region in the active area, has the first conductivity type, and has an impurity concentration higher than an impurity concentration in the drift region
Implementation Method 2
The first surface has an electrical path formed thereon, the electrical path connecting the first electrode to the end portion of the well region with a region of the second conductivity type, the electrical path having a resistance region that is formed of the well region and has a width L. The width L is set so as to suppress a local temperature rise in one of both ends of the resistance region by sharing the temperature rise at both the ends during a breaking operation
Data Source
AI summary
A semiconductor substrate includes a drift region and a collector region. The drift region is provided across an active area, an interface area, and an edge termination area. The collector region is provided only in the active area and forms part of a second surface. An emitter electrode is provided in the active area and contacts a first surface of the semiconductor substrate. A collector electrode is provided on the second surface of the semiconductor substrate and contacts the collector region.