Semiconductor Package Buffer Layer Fills Cavity Gap
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Solution Overview
Problem
The existing semiconductor packages face challenges in maintaining a thin profile while supporting mixed technology die stacking due to the formation of dimples in the gaps between embedded chips and the substrate, which hinder subsequent lamination operations and create non-uniform surfaces.
Innovation Solution
A semiconductor package design that includes a core layer with a cavity, a die embedded within, and a filling material with a buffer layer that fills the gap between the die and the substrate, providing a flat surface for subsequent lamination and using a conductive via to connect the die electrically, while an insulation layer is stacked on the buffer layer to enhance the package's structural integrity and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a filling material is used to fill the gap between the embedded die and the substrate, then the adhesive properties are enhanced, but a dimple is formed on the surface which hinders subsequent lamination operations
Solution Approach 1:
The filling process is divided into two stages: first filling the gap between the die and substrate, then performing a planarization process to create a flat surface. This segmentation allows the filling material to serve its adhesive function while eliminating the surface dimple that would hinder lamination operations.
Solution Approach 2:
The filling material is applied in advance to the gap between the die and substrate before the lamination process. This preliminary action ensures proper adhesive bonding is established, and the subsequent planarization step prepares the surface for lamination, thus resolving the conflict between adhesive enhancement and manufacturing ease.
2Strength
If the filling material is applied to fill the gap, then the adhesive properties are improved, but the surface becomes non-uniform which affects subsequent processing
Solution Approach 1:
The process is segmented into gap filling and surface planarization as separate steps. The filling material is first applied to ensure adequate adhesive properties, then a planarization process is performed to restore surface uniformity, thus satisfying both adhesive requirements and manufacturing precision needs.
Solution Approach 2:
The surface topology is changed from non-uniform (with dimple) to uniform through the planarization process. This parameter change in surface geometry allows the filling material to provide adhesive strength without compromising the uniformity required for subsequent processing steps.
3Length of stationary object
If the package profile is made thin to meet compact device requirements, then the device size is reduced, but it becomes difficult to support mixed technology die stacking
Solution Approach 1:
Multiple dies of different technologies are stacked vertically within the thin package profile, similar to nested dolls. The embedding structure allows smaller dies to be positioned within the footprint of larger dies, enabling mixed technology integration while maintaining a thin overall package thickness.
Solution Approach 2:
The solution transitions from a two-dimensional layout to a three-dimensional stacked architecture. By utilizing the vertical dimension for die stacking and embedding, the package can accommodate multiple technologies within a reduced footprint and thin profile, thus achieving both compact size and versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for efficient die stacking with a thin profile, preventing air voids and ensuring a smooth surface for lamination, thereby enhancing the adhesive properties and electrical connectivity of the semiconductor package.
Implementation Method 1
a first viscosity is smaller than the second viscosity
Data Source
AI summary
A semiconductor package includes a core layer having a first surface and a second surface opposite to the first surface. The core layer includes a cavity. A first die is in the cavity. A first gap is between a sidewall of the cavity and a sidewall of the first die. A filling material is in the first gap. The filling material includes a first dimple in proximal to the second surface of the core layer. A first buffer layer on the second surface of the core layer. The first buffer layer has a bottom surface in proximal to the first die and a top surface opposite to the bottom surface. The first buffer layer filling the first dimple. A method for manufacturing a semiconductor package is also disclosed.