Semiconductor Bump Structure Sizing to Prevent Adhesive Residue
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Solution Overview
Problem
Semiconductor devices face challenges in achieving stable electrical connections and high reliability due to the increased density of electrode terminals and reduced pitch, leading to issues such as contamination and structural instability during fabrication.
Innovation Solution
A semiconductor device design featuring a bump structure with a metal layer and solder ball, where the metal layer's width is 0.85 to 0.95 times the opening width, and a protective layer configuration that minimizes adhesive residue during fabrication, ensuring stable electrical connections and reduced contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal layer width is increased to improve electrical connection stability, then electrical connection reliability is improved, but adhesive layer residue occurs in the opening space
Solution Approach 1:
The patent applies parameter changes by precisely controlling the metal layer width to be 0.85 to 0.95 times the opening width. This specific parameter range creates an optimal balance: the metal layer is wide enough to ensure stable electrical connection and solder ball attachment, yet narrow enough to leave sufficient clearance (0.05 to 0.15 times the opening width) that prevents adhesive layer residue during the bonding process.
2Object-generated harmful factors
If the metal layer width is decreased to prevent adhesive residue, then adhesive contamination is reduced, but electrical connection stability deteriorates
Solution Approach 1:
The patent resolves this contradiction by establishing a minimum metal layer width parameter (0.85 times the opening width) that ensures sufficient electrical connection stability and solder ball attachment area, while simultaneously maintaining a maximum width (0.95 times the opening width) that preserves adequate clearance to prevent adhesive residue. This parameter optimization achieves both goals simultaneously.
3Volume of moving object
If the pitch between electrode terminals is decreased to increase device compactness, then device compactness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses manufacturing precision challenges in compact devices by optimizing the metal layer width parameter relative to the opening width. This standardized parameter relationship (0.85 to 0.95 times) ensures consistent electrical connection quality and reliable solder ball attachment even when pitch is reduced, thereby enabling device compactness while maintaining manufacturability.
Data Source
AI summary
Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a pad on a semiconductor chip, a protective layer on the semiconductor chip and having an opening that exposes a portion of a top surface of the pad, and a bump structure electrically connected to the pad. The bump structure includes a metal layer on the pad and a solder ball on the metal layer. A first width of the metal layer is about 0.85 times to about 0.95 times a second width of the opening.