Semiconductor Bus Segmentation for Electromigration Reduction
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Solution Overview
Problem
Power semiconductor devices face issues with current non-uniformity and mechanical stress due to the configuration of common buses connecting two transistors, leading to potential damage from current concentration and electromigration, as well as mechanical failure.
Innovation Solution
A semiconductor device configuration featuring two independent rectangular buses with an inter-bus interconnect that restricts current flow, reducing current concentration and mechanical stress, while allowing for space-efficient design and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a common bus is formed lying astride two transistors to connect sources or drains, then space utilization is improved and connection efficiency is enhanced, but current non-uniformity increases and electromigration damage risk increases
Solution Approach 1:
The patent divides the common bus into multiple independent bus regions, each serving specific transistors. Instead of forming a single continuous bus astride multiple transistors, the bus is segmented into separate regions with individual connections, preventing current concentration while maintaining space efficiency through optimized layout.
Solution Approach 2:
The patent applies different bus configurations to different regions based on local current requirements. Each bus region is designed with specific characteristics (width, length, position) optimized for its local transistor connections, ensuring uniform current distribution while adapting to local spatial constraints.
2Ease of operation
If a common bus is formed lying astride two transistors, then connection efficiency is improved, but mechanical stress increases and bus rupture risk increases
Solution Approach 1:
The bus is divided into separate regions rather than forming a single large continuous structure. This segmentation reduces the overall stress on any one bus region and eliminates stress concentration points that would occur in a large continuous bus spanning multiple transistors.
Solution Approach 2:
The patent introduces intermediate connection structures (such as via holes and interlayer insulating films) that mediate the mechanical stress between the bus and the transistors. These intermediary elements provide stress relief and prevent direct stress transmission that could lead to bus rupture.
3Use of energy by moving object
If bus resistance is reduced to improve current flow, then current supply efficiency is improved, but current concentration in certain bus regions increases
Solution Approach 1:
By segmenting the bus into multiple independent regions, the patent prevents current from concentrating in any single low-resistance path. Each segment handles a portion of the total current, distributing the current flow uniformly across all bus regions while maintaining overall current supply efficiency.
Solution Approach 2:
The patent optimizes the resistance characteristics of each bus region locally based on its specific current requirements. Each region can have different dimensions and materials tailored to its local needs, ensuring uniform current distribution while maintaining high overall current supply efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration ensures uniform current distribution and reduces the risk of bus damage from electromigration and mechanical stress, enhancing the reliability and performance of power semiconductor devices.
Implementation Method 1
the bus is damaged due to electromigration caused by current concentration
Data Source
AI summary
A semiconductor device includes: a first transistor; a second transistor; an interlayer insulating film covering the transistors; a rectangular-shaped first bus formed on the interlayer insulating film and connected to first source/drain regions; a rectangular-shaped second bus formed on the interlayer insulating film with spacing from the first bus and connected to third source/drain regions; an inter-bus interconnect formed between the first and second buses for connecting these buses; a first contact pad provided on the first bus, to which a wire is connected; and a second contact pad provided on the second bus, to which a wire is connected. The inter-bus interconnect is in contact with part of the side of the first bus facing the second bus and part of the side of the second bus facing the first bus. The first and second contact pads are respectively in contact with part of the first and second buses.