Semiconductor Memory Capacitor with Dual-Doped Interface Layers
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Solution Overview
Problem
Semiconductor memory devices with capacitor structures face challenges in achieving high capacity and integration due to the need for miniaturization and reduced design rules, requiring innovative capacitor dielectric layer designs to enhance capacitance.
Innovation Solution
The semiconductor memory device incorporates a capacitor dielectric layer with a lower interface layer doped with n-type impurities, a dielectric structure, and an upper interface layer doped with p-type impurities, where the dielectric structure includes a lower dielectric layer, an insertion layer with a greater bandgap, and an upper dielectric layer, stacked on the lower electrode, to create fixed polarization and increase capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the capacitor structure is miniaturized to achieve high integration, then the device density increases, but the capacitance decreases
Solution Approach 1:
The patent changes the electrical parameters of the dielectric layer by introducing dual-doped interface layers with different conductive types (n-type and p-type). This creates fixed polarization in the dielectric structure, which enhances capacitance without increasing the physical size of the capacitor, thereby resolving the contradiction between miniaturization and capacitance maintenance.
Solution Approach 2:
The patent uses a composite dielectric structure consisting of multiple layers including lower and upper interface layers doped with different impurity types, and a main dielectric layer. This composite structure creates synergistic effects where the doped interface layers generate fixed polarization that enhances the overall capacitance of the capacitor structure while maintaining small dimensions.
2Length of moving object
If the design rules are reduced for miniaturization, then the device size decreases, but the manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent segments the dielectric layer into multiple distinct layers: a lower interface layer doped with first impurities, a main dielectric layer, and an upper interface layer doped with second impurities. This segmentation allows each layer to be optimized independently for its specific function, making it easier to control the thickness and properties of each layer even under reduced design rules, thereby maintaining manufacturing precision.
Solution Approach 2:
The patent applies local quality by doping different regions of the dielectric structure with different types of impurities. The lower interface layer is doped with n-type impurities while the upper interface layer is doped with p-type impurities. This localized differentiation allows precise control over the electrical properties at specific locations within the dielectric structure, enabling accurate fabrication despite miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the capacitance of the capacitor structure, ensuring high capacity and integration in semiconductor memory devices by forming fixed polarization within the dielectric layer, thereby addressing the challenges of miniaturization and design rule reductions.
Implementation Method 1
the capacitor dielectric layer includes: a lower interface layer disposed on the lower electrode and doped with impurities of a first conductive type; an upper interface layer disposed beneath the upper electrode and doped with impurities of a second conductive type other than the first conductive type
Implementation Method 2
to create fixed polarization and increase capacitance
Implementation Method 3
an insertion layer, where a bandgap of the insertion layer is greater than each of a bandgap of the lower dielectric layer and a bandgap of the upper dielectric layer
Data Source
AI summary
A semiconductor memory device includes a substrate, and a capacitor structure on the substrate and including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the capacitor dielectric layer includes a lower interface layer on the lower electrode and doped with impurities of a first conductive type, an upper interface layer beneath the upper electrode and doped with impurities of a second conductive type other than the first conductive type, and a dielectric structure between the lower interface layer and the upper interface layer.