Semiconductor Capping Pattern Alignment via Carbon Filling Insulation
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to reduce capacitance and ensure electrical stability as feature sizes decrease, requiring minimization of etching in the active region to align the top surface of the capping pattern with the element isolation region, thereby simplifying the process of forming gate contacts.
Innovation Solution
A semiconductor device and method where the top surface of the capping pattern in the active region is formed at the same level as the element isolation region by minimizing etching, incorporating a filling insulating layer with carbon atoms to facilitate this alignment and reduce the complexity of forming gate contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching is performed to form source/drain contact, then source/drain contact is formed, but the capping pattern in the active region is etched causing top surface misalignment with the element isolation region
Solution Approach 1:
A filling insulating layer is introduced as an intermediary material to fill the contact trench after source/drain contact formation. This filling layer compensates for the etching damage to the capping pattern, restoring the top surface alignment between the active region and element isolation region without requiring complex re-etching or adjustment processes.
Solution Approach 2:
The method changes the physical state and composition parameters of the contact trench by filling it with an insulating material after contact formation. This parameter change (from empty/etched trench to filled trench with restored top surface) compensates for the etching-induced misalignment and simplifies subsequent gate contact formation processes.
2Productivity
If feature size is decreased for high integration, then device integration increases, but capacitance increases and electrical stability decreases
Solution Approach 1:
The filling insulating layer is applied locally to the contact trench region, providing localized electrical isolation and stability enhancement. This local quality improvement addresses the capacitance and electrical stability issues in the contact region without affecting the overall device scaling and integration benefits.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.