Semiconductor Device Carrier Lifetime Control via Segmented Regions
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Solution Overview
Problem
Semiconductor devices, such as IGBTs, face challenges in improving leak current characteristics and other performance metrics due to limitations in existing designs.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a drift region, a transistor portion, and an adjacent element portion, featuring trench portions, conducting portions, and lifetime control regions to optimize conductivity and carrier lifetime management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single lifetime control region is provided in conventional semiconductor devices, then manufacturing process is simple, but carrier lifetime control precision is insufficient leading to poor leak current characteristics
Solution Approach 1:
The lifetime control structure is divided into multiple lifetime control regions (first, second, and third regions) positioned at different depths within the drift region. Each region contains lifetime killers that control carrier lifetime at specific depth zones, enabling precise control of leak current characteristics through segmented depth-wise management rather than a single uniform control region.
Solution Approach 2:
The invention transitions from controlling carrier lifetime in a single planar region to three-dimensional depth-stratified control by positioning lifetime control regions at different depths (first, second, and third regions) within the drift region. This vertical dimensionality enables independent optimization of leak current suppression at different depth zones, resolving the contradiction between control precision and structural complexity.
2Power
If carrier lifetime is extended to improve ON voltage characteristics, then turn-off power loss increases due to prolonged carrier storage
Solution Approach 1:
Different regions of the drift region are assigned different carrier lifetime characteristics through the placement of lifetime killers in specific lifetime control regions. The first lifetime control region maintains longer carrier lifetime for low ON voltage, while the second and third regions with lifetime killers provide localized lifetime reduction to accelerate carrier removal during turn-off, thereby reducing turn-off power loss. This local differentiation resolves the trade-off between ON voltage and turn-off loss.
Solution Approach 2:
The invention changes the carrier lifetime parameter spatially by introducing lifetime killers in specific depth regions. By controlling the concentration and distribution of lifetime killers in the second and third lifetime control regions, the carrier lifetime is dynamically adjusted: longer lifetime in the first region for low ON voltage operation, and shorter lifetime in deeper regions for rapid carrier extraction during turn-off, optimizing both power characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the semiconductor device's performance by improving leak current suppression and tradeoff between ON voltage and turn-off power loss, while maintaining effective carrier lifetime management.
Implementation Method 1
a first lower surface side lifetime control region (74) that is provided, on a lower surface side of the semiconductor substrate, continuously from the transistor portion (70) to the adjacent element portion (80) and includes a lifetime killer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a drift region of a first conductivity type, a transistor portion provided in the substrate, and an adjacent element portion provided in the substrate, the adjacent element and transistor portions being arranged along an arrangement direction. The transistor and adjacent element portions both include a base region of a second conductivity type provided above the drift region, trench portions formed through the base region, extending in an extending direction orthogonal to the arrangement direction on the upper surface, and having a conducting portion therein, and a first lower surface side lifetime control region provided, on a lower surface side, continuously from the transistor portion to the adjacent element portion and includes a lifetime killer. The lifetime control region is provided over entirety of the transistor portion and in a part of the adjacent element portion in a top view of the substrate.