Semiconductor Carrier with Additive Metalized Pattern for Fine Pitch Routing
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Solution Overview
Problem
Conventional semiconductor packages face limitations in routing capability and inner lead pitch due to the etching process, which restricts the fabrication of sufficiently small lead frames while maintaining structural strength.
Innovation Solution
A method involving the deposition of conductive vias on a lead frame, application of molding material, grinding to expose vias, and deposition of a metalized pattern for electrical communication, along with etching and additional features like a seed layer and fiducial marks, to enhance the carrier's electrical interconnections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used to fabricate lead frame, then manufacturing process is simple, but routing capability is limited and inner lead pitch cannot be sufficiently reduced
Solution Approach 1:
The lead frame structure is segmented into multiple functional layers: the base lead frame structure and the additively formed metalized pattern layer. This segmentation allows the pitch-critical features to be formed in a separate layer with different manufacturing constraints, enabling finer pitch without compromising the structural integrity of the bulk lead frame.
Solution Approach 2:
The solution transitions from a planar two-dimensional lead frame design to a three-dimensional multi-layer structure. By adding the metalized pattern layer on top of the molding material that covers the lead frame, the patent creates vertical stacking of conductive paths, enabling reduced pitch through spatial redistribution across multiple dimensions.
2Manufacturing precision
If lead frame size is reduced to achieve narrower pitch, then routing capability improves, but structural strength decreases leading to deformation and damage
Solution Approach 1:
The patent separates the structural support function from the fine-pitch interconnection function. The bulk lead frame maintains its structural strength while the fine-pitch routing is achieved through the additively formed metalized pattern on the molding material, allowing independent optimization of both strength and pitch.
Solution Approach 2:
The molding material serves as an intermediary substrate that supports the metalized pattern layer. This intermediary allows the formation of narrow pitch features without requiring the entire lead frame to be miniaturized, thus maintaining overall structural strength while achieving fine pitch in specific routing areas.
3Adaptability or versatility
If conventional lead frame structure is used, then manufacturing is straightforward, but routing capability from chip to carrier is not available
Solution Approach 1:
The conductive vias are pre-formed on the lead frame before the molding process, and the metalized pattern is additively formed after molding. This preliminary preparation of conductive pathways enables subsequent chip mounting with proper electrical interconnections, enhancing routing capability while maintaining manufacturing efficiency through staged processing.
Solution Approach 2:
The patent introduces vertical conductivity through the molding material by forming conductive vias and adding a metalized pattern layer on top. This three-dimensional approach to routing enables electrical connections that pass through the molding material, providing routing capability that was not available in conventional planar lead frame structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of carriers with improved routing capabilities and narrower lead structures, enabling the use of chips with more contacts and enhanced structural strength, thereby overcoming the limitations of conventional etching techniques.
Implementation Method 1
depositing a plurality of conductive vias on a top surface of a lead frame
Implementation Method 2
applying a molding material over the lead frame, wherein the molding material covers the top surface of the lead frame
Implementation Method 3
grinding the molding material to expose the plurality of conductive vias
Implementation Method 4
depositing a metalized pattern over the molding material, wherein the metalized pattern is in electrical communication with the plurality of conductive vias
Implementation Method 5
etching the lead frame with dual rows of leads
Implementation Method 6
depositing a seed layer on the molding material prior to depositing the metalized pattern
Data Source
AI summary
A method of manufacturing, a carrier, and a semiconductor package are provided. The method involves depositing a plurality of conductive vias, applying a molding material over the lead frame, grinding the molding material to expose the plurality of conductive vias, and depositing a metalized pattern over the molding material. The carrier is manufacture by this method and the semiconductor package is formed based on the carrier.