Semiconductor Device Carrier Wafer Singulation Yield
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Solution Overview
Problem
The cumulative defect rate in wafer stacking methods leads to reduced product yield and increased costs in semiconductor manufacturing, particularly in three-dimensional package applications where multiple dies are integrated.
Innovation Solution
A method involving the use of a carrier wafer and temporary bond to thin and singulate dies, allowing for selective bonding of known good dies (KGDs) to a host substrate, thereby preventing defects and improving yield, and using through-silicon vias and dielectric layers for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the W2W method is used to stack wafers before dicing, then manufacturing efficiency is improved, but defect rate increases cumulatively with increasing number of stacked wafers
Solution Approach 1:
The process is segmented into two independent stages: (1) singulation of individual dies from donor wafers before bonding, and (2) stacking of pre-singulated dies. This segmentation prevents defect accumulation by isolating the singulation process from the stacking process, allowing only verified good dies to be stacked.
Solution Approach 2:
The singulation of dies is performed as a preliminary action before the stacking process. By pre-singulating and verifying dies on donor wafers, the system ensures that only known good dies are stacked, eliminating the cumulative defect problem that occurs when stacking entire wafers.
2Adaptability or versatility
If multiple wafers are stacked together, then three-dimensional package applications are enabled, but defect rate rises cumulatively leading to fall in product yield
Solution Approach 1:
Donor wafers serve as intermediaries that hold and protect multiple dies during the singulation and transfer process. The donor wafer allows individual dies to be singulated, tested, and then transferred to the stack one by one, ensuring that only verified good dies are included in the final three-dimensional package.
Solution Approach 2:
Dies are pre-singulated and pre-verified on donor wafers before being stacked. This preliminary verification ensures that only known good dies are used in the three-dimensional package, maintaining high yield even when stacking multiple layers.
3Productivity
If wafers are stacked before dicing, then dicing after stacking is performed, but defect accumulation leads to rise in final product cost
Solution Approach 1:
The manufacturing process is segmented so that only the necessary number of good dies are singulated and stacked, rather than processing entire wafers. This reduces waste and rework costs associated with defective dies, thereby lowering final product cost while maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing efficiency by reducing defect accumulation, improving product yield, and enabling the integration of diverse dies in multi-chip packages with reduced backside chipping and mechanical stress, thus lowering final product costs.
Implementation Method 1
attaching a carrier wafer to a front side of a top die wafer
Implementation Method 2
using through-silicon vias and dielectric layers for electrical connectivity
Data Source
AI summary
The present disclosure relates to a semiconductor device and method of manufacturing the same. The method for manufacturing a semiconductor device includes: attaching a carrier wafer to a front side of a top die wafer; thinning a back side of the top die wafer, the back side of the top die wafer being opposite to the front side the top die wafer; singulating the carrier wafer and the top die wafer whereby singulated dies attached to singulated carrier dies are formed; and bonding back side of each of the singulated dies to a front side of a bottom die wafer.