Semiconductor Cell Geometry for Parasitic BJT Prevention

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Solution Overview

Problem

Prior art MOSFET devices have limited pitch reduction due to a short region next to the source region, which increases cell size and degrades blocking voltage, and use suboptimal contact metals for source and body regions of opposite conductivity types.

Innovation Solution

The improved semiconductor device geometry features a short region separated from the source region by a body region, allowing for shared short regions between cells, and uses different metals for source and short contacts to optimize conductivity, with the short region in ohmic contact with the body region through strips that interrupt the JFET region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a short region is placed next to the source region to prevent parasitic BJT activation, then blocking voltage is maintained, but cell pitch increases and on-resistance increases

Engineering Contradiction:

Improveblocking voltageVSAvoidcell pitch

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The short region is extracted from its traditional position adjacent to the source region and relocated to the JFET region. This separation removes the space-consuming short region from the critical source-body area, allowing cell pitch reduction while maintaining the short region's function of preventing parasitic BJT activation through proper potential clamping

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The short region is repositioned from a lateral adjacency relationship to the source region to a position within the JFET region, utilizing the vertical and lateral space in the JFET area. This dimensional reconfiguration allows the short region to serve its protective function without occupying宝贵 space in the source-body region, thereby reducing cell pitch

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If a shared contact metal is used for both source and short contacts, then manufacturing is simplified, but contact performance deteriorates due to suboptimal metal selection for opposite conductivity types

Engineering Contradiction:

Improvecontact fabricationVSAvoidcontact conductivity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Different contact metals are applied to the source contact and short contact regions based on their respective conductivity types. The source contact uses metal optimized for N-type semiconductor, while the short contact uses metal optimized for P-type semiconductor. This localized differentiation ensures optimal electrical contact performance at each interface, improving overall device reliability despite increased fabrication complexity

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces cell pitch, decreases 'on' resistance, and maintains stable breakdown voltage by preventing parasitic BJT activation and optimizing contact metals for each region's conductivity type.

Implementation Method 1

The short from source to the body region prevents the activation of the parasitic Bipolar Junction Transistor (BJT) allowing reverse current flow between the drain and the source

Methodology Applied

Scientific EffectParasitic BJT activation prevention:

Implementation Method 2

A channel area is formed at the contact boundary between then the body region and an epitaxial layer Junction Field Effect Transistor (JFET) region where charge and carrier combine to allow current to flow through the device

Methodology Applied

Scientific EffectJunction Field Effect:

Implementation Method 3

The short region is in ohmic contact with the body region through strips that interrupt the JFET region

Methodology Applied

Scientific EffectOhmic contact:

Data Source

PatentUS11616123B2Enhancement on-state power semiconductor device characteristics utilizing new cell geometries

Publication Date: 2023.03.28 ALPHA & OMEGA SEMICON INT LP

AI summary

A semiconductor device and a method of making thereof are disclosed. The device includes a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type formed on the substrate. A buffer layer between the substrate and the epitaxial layer is doped with the first conductivity type at a doping level between that of the substrate and that of the epitaxial layer. A cell includes a body region doped with the second conductivity formed in the epitaxial layer. The second conductivity type is opposite the first conductivity type. The cell includes a source region doped with the first conductivity type and formed in at least the body region. The device further includes a short region doped with the second conductivity type formed in the epitaxial layer separated from source region of the cell by the body region of the cell wherein the short region is conductively coupled with the source region.