Semiconductor Cell Layout for Faster Mixed-Row Legalization

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Solution Overview

Problem

Conventional automatic placement and routing (APR) processes struggle to efficiently legalize integrated circuit designs with mixed-row heights, leading to increased processing time.

Innovation Solution

A method for integrated circuit design layout that includes a pre-process stage to alter cell versions and a legalization process to rearrange cells, reducing cell congestion and overlap, while maintaining legal placement sites, using a Monte-Carlo based algorithm to optimize cell versions and positions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional APR legalization process is used for mixed-row height designs, then all cell rows are legalized, but the total operating time of the APR process increases significantly

Engineering Contradiction:
Improvelegalization completenessVSAvoidAPR process operating time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the layout into multiple regions and processes each region separately using a sliding window approach. Instead of legalizing the entire layout at once, the method segments the problem into manageable chunks, processing cells in overlapping windows that move across the layout. This segmentation reduces the computational complexity and processing time while maintaining legalization quality in each region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-processing the layout to identify and mark cells that are likely to cause conflicts before the main legalization process. The method also pre-calculates conflict information and prepares data structures in advance, which accelerates the subsequent legalization steps and reduces overall processing time.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If mixed-row height design is used, then area optimization is achieved, but the APR legalization process becomes less efficient

Engineering Contradiction:
Improvechip areaVSAvoidlegalization processing speed
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent applies local quality by allowing different row heights in different regions of the layout to optimize area utilization. The method preserves the mixed-row height structure where beneficial for area optimization while applying targeted legalization strategies in specific regions. This localized approach maintains area efficiency without requiring uniform row heights across the entire chip.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces dynamics by making the legalization process adaptive to local conditions. The sliding window approach dynamically adjusts the processing focus to regions with conflicts, and the method dynamically selects which cells to move based on local density and conflict patterns. This dynamic behavior allows the algorithm to efficiently handle mixed-row height variations without being constrained by a rigid uniform approach.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If uniform row height is assumed in legalization, then processing is simpler, but area optimization opportunities are lost

Engineering Contradiction:
Improvelegalization process complexityVSAvoidchip area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent segments the layout into regions with consistent row height characteristics, processing each segment with appropriate assumptions. This segmentation allows the method to handle mixed-row height designs by treating each homogeneous region separately, reducing the effective complexity of the legalization process while preserving area optimization opportunities across the entire layout.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250307517A1Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor device
Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250307517A1 patent drawing
  • US20250307517A1 patent drawing
  • US20250307517A1 patent drawing

AI summary

The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout, wherein the cells each include a first cell version and a second cell version different from the first cell version; (b) dividing the first layout into a plurality of regions; (c) calculating a first density of each of the plurality of regions; (d) calculating, for a first region of the plurality of regions, a first probability of altering cell versions for cells in the first region according to the first density of the first region; (e) altering cell versions of one or more cells in the first region according to a comparison between the first probability and a first threshold; and (f) rearranging the cells in the first layout to reduce cell overlap.