Semiconductor Cell Through Holes via Impurity-Doped Etch Rate Control
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Solution Overview
Problem
The reduction in design rule shrinkage for semiconductor devices leads to increased contact resistance and internal resistance in electric nodes due to smaller through hole diameters, causing electrical short-circuits and deteriorating the semiconductor cell structure's electrical characteristics.
Innovation Solution
A method of forming a semiconductor cell structure with through holes surrounded by insulating layers of different etch rates, using a concentration gradient of impurity ions in the third insulating layer and applying specific etchants to stabilize the through hole diameters and prevent exposure of conductive patterns, thereby improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the design rule is continuously reduced to shrink the distance between conductive patterns, then the integration density is improved, but the through hole diameter becomes smaller causing increased contact resistance and internal resistance
Solution Approach 1:
The patent changes the etch rate parameter of the insulating layer by introducing a concentration gradient of impurity ions (such as boron or phosphorus) within the insulating layer. This creates regions with different etch rates, allowing the through hole to be selectively enlarged in specific zones while maintaining precise control over the hole's shape and size, thereby reducing contact resistance without compromising the shrunk design rule
Solution Approach 2:
The patent applies local quality by creating a non-uniform impurity concentration distribution within the insulating layer. The impurity concentration varies spatially, with higher concentrations in regions where faster etching is desired to enlarge the through hole diameter, and lower concentrations in regions where slower etching is needed to maintain precision. This localized variation in material properties enables selective hole enlargement to improve electrical characteristics
2Length of stationary object
If the through hole diameter is reduced due to design rule shrinkage, then the distance between conductive patterns is reduced, but the contact resistance and internal resistance increase
Solution Approach 1:
The patent modifies the etch rate parameter of the insulating layer through impurity doping, creating a concentration gradient that enables selective enlargement of the through hole diameter. This parameter change allows the through hole to be larger than what would be defined by the design rule alone, thereby reducing contact resistance while maintaining the shrunk pitch between conductive patterns
Solution Approach 2:
The patent performs preliminary action by pre-doping the insulating layer with impurity ions before the through hole formation process. This preliminary modification of the insulating layer's etch characteristics ensures that during subsequent etching, the through hole automatically enlarges to an optimal diameter that reduces contact resistance, without requiring additional post-processing steps
3Duration of action of stationary object
If the through hole passes through the lower insulating layer to extend towards it, then the upper insulating layer is fully penetrated, but the conductive patterns are exposed causing electrical short-circuit
Solution Approach 1:
The patent applies local quality by creating spatial variation in the insulating layer's etch resistance through non-uniform impurity distribution. The etch rate is locally modified so that the through hole etches faster in regions where insulating material needs to be removed, while slower in regions near the lower conductive patterns. This prevents over-etching and exposure of conductive patterns, avoiding electrical short-circuits
Solution Approach 2:
The patent uses the impurity-doped insulating layer as an intermediary that mediates the etching process. The impurity concentration gradient acts as a buffer that controls the etch front propagation, allowing the through hole to penetrate the upper insulating layer completely while automatically stopping before exposing the lower conductive patterns, thus preventing short-circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes through hole diameters and reduces contact resistance, enhancing the electrical characteristics of semiconductor devices and modules by minimizing leakage currents and preventing electrical short-circuits.
Implementation Method 1
The third insulating layer may be etched at least twice and the second insulating layer at least once to form a through hole
Implementation Method 2
the etch stopping layer having a different etch rate from the lower insulating layer and the remaining upper insulating layer
Data Source
AI summary
In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.