3D Memory Semiconductor Device Channel Layer Segmentation
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Solution Overview
Problem
Existing methods for electrically connecting a channel semiconductor layer with an interconnection in three-dimensional memory devices are inefficient, leading to poor operation due to carrier electrons' difficulty in reaching channel semiconductor layers with deep channel body layers.
Innovation Solution
A semiconductor device structure where a thin semiconductor layer is formed on the surface of projected portions of the channel semiconductor layer and source interconnection layer, allowing for direct electrical connection and improving carrier path formation, with the semiconductor layer being 10 nm or less in thickness to ensure effective charge storage and inversion layer generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a deep channel body layer is used in three-dimensional memory, then data storage capacity is improved, but carrier electrons have difficulty reaching the channel semiconductor layer leading to poor operation
Solution Approach 1:
The patent segments the channel body layer into multiple thin semiconductor layers (first semiconductor layer, second semiconductor layer, etc.) stacked in the thickness direction. Each layer has a thickness of 10 nm or less, which allows carrier electrons to effectively reach and interact with each layer, solving the problem of poor operation in deep channel structures while maintaining high storage capacity through the stacked configuration.
Solution Approach 2:
The patent transitions from a single deep channel body layer to multiple thin layers stacked in the vertical dimension. This dimensional approach allows the memory structure to achieve deep effective storage depth while maintaining shallow individual layer depths that enable effective carrier electron interaction, thus resolving the contradiction between storage capacity and operation efficiency.
2Reliability
If a thin semiconductor layer of 10 nm or less is used, then electrical connection efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a precise thickness parameter of 10 nm or less for the semiconductor layers to optimize electrical connection efficiency and carrier electron interaction. This parameter control is achieved through advanced thin film deposition techniques, balancing the need for thin layers with manufacturing capabilities.
Solution Approach 2:
The patent applies different quality requirements to different parts of the structure: the semiconductor layers require high precision thickness control (10 nm or less) for optimal electrical performance, while other structural elements can have more relaxed tolerances. This localized quality approach manages manufacturing complexity while achieving the required performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables preferable operation of three-dimensional memory devices by ensuring efficient electrical connection and reducing cell current variations, preventing 'cut-off' issues and allowing for effective data erasure.
Implementation Method 1
a thin semiconductor layer is formed on the surface of projected portions of the channel semiconductor layer and source interconnection layer, allowing for direct electrical connection and improving carrier path formation
Data Source
AI summary
In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.