Semiconductor Storage Device Channel Layer Shape Integrity
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Solution Overview
Problem
The challenge in three-dimensional semiconductor memory devices is to maintain the shape integrity of the channel semiconductor layer while reducing its thickness to improve memory cell characteristics, as thinner layers can lead to shape abnormalities and difficulties in pillar portion embedding due to potential hole generation and abnormal growth of layers.
Innovation Solution
The semiconductor storage device design includes a second insulating layer with a narrower width than the stacked film, featuring a channel semiconductor layer with varying thickness regions to prevent shape abnormalities, where the thickness is increased in the vicinity of the second insulating layer to avoid hole formation while maintaining the pillar portion openings open, and the second insulating layer's narrower width prevents closure of these openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the channel semiconductor layer is reduced to improve memory cell characteristics, then the memory cell characteristics are improved, but shape abnormalities occur in the vicinity of the channel semiconductor layer
Solution Approach 1:
The patent applies local quality by making the channel semiconductor layer thickness non-uniform: thinner in the main body region to improve memory characteristics, and thicker in the vicinity of the second insulating layer to prevent shape abnormalities. This localized variation in thickness resolves the contradiction between improving memory cell characteristics and maintaining shape integrity.
2Reliability
If the thickness of the channel semiconductor layer is reduced, then memory cell characteristics are improved, but hole generation and abnormal growth of layers occur making pillar portion embedding difficult
Solution Approach 1:
The patent uses local quality by varying the channel semiconductor layer thickness locally - maintaining thinner thickness in most regions for improved memory characteristics while increasing thickness specifically in the vicinity of the second insulating layer. This prevents hole generation and abnormal layer growth that would otherwise make pillar portion embedding difficult.
Solution Approach 2:
The patent applies preliminary action by pre-forming the second insulating layer with a narrower width before forming the channel semiconductor layer. This preliminary structuring prevents subsequent abnormalities during manufacturing, ensuring that the channel semiconductor layer forms correctly without holes or abnormal growth that would hinder pillar portion embedding.
3Ease of manufacture
If the second insulating layer has the same width as the stacked film, then manufacturing is simpler, but openings may close due to abnormal growth of the channel semiconductor layer
Solution Approach 1:
The patent applies preliminary action by forming the second insulating layer with a narrower width than the stacked film before subsequent manufacturing steps. This preliminary dimensioning prevents the channel semiconductor layer from abnormally growing and closing the openings, while not significantly complicating the manufacturing process.
Solution Approach 2:
The patent uses preliminary anti-action by designing the second insulating layer with a narrower width to counteract the potential abnormal growth of the channel semiconductor layer. This preemptive dimensional constraint prevents the openings from closing, addressing the problem before it can occur during manufacturing.
Data Source
AI summary
In one embodiment, a semiconductor storage device includes a substrate, a stacked film including a plurality of first insulating layers and a plurality of electrode layers that are alternately provided on the substrate, and a second insulating layer provided on the stacked film. The device further includes a plurality of pillar portions, each of which including a first insulator, a charge storage layer, a second insulator, a first semiconductor layer and a third insulator that are sequentially provided in the stacked film and the second insulating layer. Furthermore, a width of the second insulating layer sandwiched between the pillar portions is narrower than a width of the stacked film sandwiched between the pillar portions, in at least a portion of the second insulating layer.