3D Semiconductor Channel Structure With Si/SiGe Mobility Tuning
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Solution Overview
Problem
The increasing demand for high performance, high speed, and multifunctionality in semiconductor apparatuses has led to limitations in operating properties due to the reduction in size of planar metal oxide semiconductor field effect transistors (MOSFETs), necessitating the development of alternative transistor structures like gate-all-around type FETs and FinFETs.
Innovation Solution
A semiconductor apparatus is designed with a substrate featuring a first and second region, including a channel structure with insulating isolation patterns and semiconductor patterns, source/drain patterns, and gate structures, utilizing silicon and silicon germanium materials with varying germanium concentrations to enhance carrier mobility and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOSFET size is reduced to increase integration density, then integration density is improved, but operating properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional structures including FinFETs with vertical fins and gate-all-around FETs with nanosheets surrounded by gates on all sides. This dimensional change enables better gate control over the channel while maintaining small footprint, thus improving operating properties without sacrificing integration density.
Solution Approach 2:
The patent employs composite material structures including semiconductor-sacrificial semiconductor stacks where alternating layers of different materials (e.g., Si/SiGe) are used. The sacrificial layers are selectively removed to form suspended nanosheets or fins, creating complex 3D channel structures that enhance carrier mobility and gate control while maintaining high integration density.
2Ease of manufacture
If conventional semiconductor structures are used, then manufacturing process is simple, but carrier mobility is limited
Solution Approach 1:
The patent modifies material parameters by using silicon germanium (SiGe) with varying germanium concentrations in sacrificial layers and channel structures. By controlling the germanium content and creating graded compositions, the patent enhances carrier mobility through strain engineering while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The patent uses composite semiconductor structures with alternating layers of silicon and silicon germanium. These composite stacks are processed to create suspended nanosheets or fins where the different materials provide complementary properties: silicon for high mobility channels and SiGe for sacrificial or stress-induced mobility enhancement layers.
Data Source
AI summary
A semiconductor apparatus may include a substrate including a first region and a second region; a first device on the first region; and a second device on the second region. The first device may include a channel structure including an insulating isolation pattern, first semiconductor patterns stacked under a lower surface of the insulating isolation pattern and including silicon germanium, and second semiconductor patterns stacked on an upper surface of the insulating isolation pattern and including silicon. The second device may include a semiconductor stack at a level corresponding to a level of the channel structure. The semiconductor stack may include an intermediate semiconductor layer, first lower semiconductor layers and second lower semiconductor layers alternately stacked under a lower surface of the intermediate semiconductor layer, and first upper semiconductor layers and second upper semiconductor layers alternately stacked on an upper surface of the intermediate semiconductor layer.