Semiconductor Chip Arrays Bond-Then-Dice Fiducial Alignment
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Solution Overview
Problem
Conventional methods for forming two-dimensional and three-dimensional semiconductor arrays face challenges such as inconsistencies in pixel density, large gaps between chips, and high material scrap rates, leading to increased costs and lost information due to defects and tolerance issues.
Innovation Solution
A bond-then-dice process is employed, using fiducials for precise alignment and removal of sacrificial edges to form tightly packed arrays without gaps, allowing for systematic formation of large area arrays with minimal material waste and improved chip placement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dicing and die placement methods are used to form chip arrays, then chip assembly is achieved, but inconsistencies in pixel distance at chip edges create gaps in captured images
Solution Approach 1:
The patent performs dicing to remove sacrificial edges and create precise pixel-to-edge distances before chip bonding. This preliminary action ensures that when chips are placed adjacent to each other, the pixels at the edges are equidistant from the chip boundaries, eliminating gaps in the captured image and ensuring consistent pixel spacing across the entire array.
2Extent of automation
If chips are stacked on top of each other or positioned relative to a board, then three-dimensional arrays are formed, but large gaps appear due to tolerance issues in alignment
Solution Approach 1:
The patent performs dicing to remove sacrificial edges and create precise pixel-to-edge distances before chip bonding. This preliminary action ensures that when chips are placed adjacent to each other, the pixels at the edges are equidistant from the chip boundaries, eliminating gaps in the captured image and ensuring consistent pixel spacing across the entire array.
3Measurement precision
If a single chip is formed per wafer to achieve very large arrays, then high resolution is obtainable, but material scrap rate increases due to wafer defects
Solution Approach 1:
The patent segments the wafer into multiple chips during the dicing process, rather than forming a single large array per wafer. This allows individual chips to be tested and selected, so that wafers with defects can still yield usable chips. The segmentation enables multiple smaller arrays to be formed from a single wafer, reducing material waste while maintaining the capability to form large arrays by combining multiple chips.
Data Source
AI summary
A sensor chip formed from a plurality of sensor chips fabricated on a wafer, the wafer including a top surface, a bottom surface opposite the top surface and a thickness between the top and bottom surfaces, the sensor chip including an active area formed on the top surface, a first sacrificial edge including a first fiducial and a second fiducial, and a first score line formed in a first portion of the thickness on the top surface between the first sacrificial edge and the active area.