Semiconductor Chip Backside Metallization for Solder Void Control

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Solution Overview

Problem

Existing semiconductor chip packaging technologies limit chip size due to die pad constraints, requiring costly solutions or increasing the risk of solder voids and active area reduction when attempting to use larger-than-standard chips.

Innovation Solution

Incorporating a structured backside metallization with a solder stop region that is recessed or has lower wettability, allowing for increased chip size without exceeding die pad limits, and using this metallization to control die attach material bleedout, thereby enabling larger chip sizes with minimal impact on assembly costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If a larger-than-standard chip is used, then chip size is increased, but the risk of solder voids and gate solder issues increases

Engineering Contradiction:
Improvechip sizeVSAvoidsolder void risk
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a structured backside metallization with different regions having distinct properties: a contact portion with higher wettability for reliable solder attachment, and a stop region with lower wettability to prevent solder bleedout. This localized differentiation allows larger chip sizes while maintaining solder joint reliability and preventing the formation of solder voids.

Inventive Principle:
Principle #3Local quality

2Area of moving object

If a larger-than-standard chip is used, then chip size is increased, but active area reduction occurs due to flip chip design rules

Engineering Contradiction:
Improvechip sizeVSAvoidactive area
Core Design Contradiction:
Area of moving objectVSArea of stationary object

Solution Approach 1:

The patent utilizes the backside dimension of the chip to implement the structured metallization with contact and stop regions. By working on the backside surface rather than the front active area, the design allows larger chip dimensions without encroaching on the active circuit area, thus maintaining full active area utilization while enabling increased overall chip size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of moving object

If a larger-than-standard chip is used, then chip size is increased, but assembly cost increases

Engineering Contradiction:
Improvechip sizeVSAvoidassembly cost
Core Design Contradiction:
Area of moving objectVSEase of manufacture

Solution Approach 1:

The patent changes the wettability parameter of the backside metallization surface through selective material deposition or surface treatment in different regions. This parameter modification creates the contact portion with high wettability and stop region with low wettability, enabling controlled solder flow behavior that supports larger chip sizes using standard assembly processes and materials, thereby avoiding increased assembly costs.

Inventive Principle:
Principle #35Parameter changes

4Area of moving object

If clearance between die pad edge and chip edge is maintained, then chip size is limited, but solder bleedout control is ensured

Engineering Contradiction:
Improvechip sizeVSAvoidsolder bleedout control
Core Design Contradiction:
Area of moving objectVSEase of manufacture

Solution Approach 1:

The patent introduces an intermediary structure - the structured backside metallization with stop regions - that acts as a mediator between the chip and die pad. This intermediary controls solder bleedout through its low-wettability stop regions, allowing the chip to extend closer to or beyond the die pad edges while maintaining proper solder containment, thus enabling larger chip sizes without compromising solder control.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for a significant increase in chip size, up to 25-40%, while maintaining cost-effectiveness and reducing the risk of solder voids and chip cracking, by using copper backside metallization and controlling die attach material flow.

Implementation Method 1

the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion

Methodology Applied
Scientific EffectWettability: Wetting

Data Source

PatentUS20230230903A1Semiconductor chip, chip system, method of forming a semiconductor chip, and method of forming a chip system
Publication Date: 2023.07.20 INFINEON TECHNOLOGIES AG
  • US20230230903A1 patent drawing
  • US20230230903A1 patent drawing
  • US20230230903A1 patent drawing

AI summary

A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.