Semiconductor Chip Contact Elements with Insulating Conductive Layers
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in effectively integrating power semiconductor chips with vertical structures and managing heat dissipation while maintaining electrical insulation and conductivity.
Innovation Solution
The use of a carrier with an electrically insulating layer and an electrically conductive layer, where the insulating layer is thermally conductive and provides high blocking capability, and the conductive layer establishes connections between semiconductor chips and pins, allowing for efficient heat dissipation and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an electrically insulating layer is used to provide electrical isolation between semiconductor chips and carrier, then electrical insulation is improved, but thermal dissipation capability deteriorates
Solution Approach 1:
The patent employs a composite layer structure consisting of an electrically insulating layer with thermal conduction properties and an electrically conductive layer with thermal conduction properties. This composite structure simultaneously provides electrical insulation while enabling thermal dissipation, resolving the contradiction between electrical isolation and heat management.
2Reliability
If an electrically conductive layer is added to establish electrical connections between chips and pins, then electrical connectivity is improved, but device structure complexity worsens
Solution Approach 1:
The electrically conductive layer serves multiple functions: it provides electrical connectivity between semiconductor chips and pins, and simultaneously contributes to thermal dissipation. This multi-functionality reduces the need for separate dedicated thermal management structures, thereby limiting the increase in device complexity.
3Reliability
If power semiconductor chips with vertical structures are integrated, then functional performance is improved, but integration difficulty worsens
Solution Approach 1:
The patent divides the thermal management and electrical isolation functions into distinct layers: an electrically insulating layer for electrical isolation and an electrically conductive layer for both electrical connectivity and thermal dissipation. This segmentation allows power semiconductor chips with vertical structures to be integrated more easily by providing clear interfaces and simplified assembly processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reliable integration of power semiconductor chips with vertical structures, effective heat management, and secure electrical connections, enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
an electrically insulating layer (2) arranged over the carrier (1)
Implementation Method 2
the insulating layer is thermally conductive and provides high blocking capability
Implementation Method 3
the conductive layer establishes connections between semiconductor chips and pins
Data Source
AI summary
A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.