Semiconductor Chip Island Cavities for Solder Placement

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Solution Overview

Problem

Surface mount devices face challenges in solder placement, which can lead to increased electrical resistance and limited electrical performance due to excessive solder thickness and coverage, making it difficult to achieve optimal electrical connections between the device and the printed circuit board.

Innovation Solution

A semiconductor device with a chip island and encapsulation material, featuring cavities on the second main face to receive solder, allowing for controlled solder placement and alignment with through-openings in the circuit board, enabling efficient electrical connections and reduced conduction distance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder is applied to the surface mount device, then the device can be attached to the printed circuit board, but the solder coverage may be excessive and increase electrical resistance

Engineering Contradiction:
Improveattachment reliabilityVSAvoidsolder placement precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The solder mask is divided into multiple discrete openings (first opening, second opening, third opening) that correspond to specific solder ball locations. This segmentation allows precise control of solder placement areas, preventing excessive solder coverage while ensuring reliable attachment to the printed circuit board.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the solder mask have different properties: the openings provide solder access areas while the surrounding mask material prevents solder spread. This local differentiation ensures solder is applied only where needed, controlling both attachment reliability and electrical resistance.

Inventive Principle:
Principle #3Local quality

2Strength

If solder thickness is increased to ensure good attachment, then mechanical strength improves, but electrical resistance increases

Engineering Contradiction:
Improveattachment strengthVSAvoidsolder thickness control
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The solder mask openings are designed with specific dimensions that control solder thickness. The segmented opening structure allows precise control of solder volume and thickness, ensuring adequate attachment strength while maintaining low electrical resistance through optimized solder dimensions.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the chip island area is increased to provide more solder coverage, then attachment reliability improves, but the device area increases

Engineering Contradiction:
Improveattachment reliabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The chip island is functionally segmented into an active chip area and a solder ball array area. The solder mask further segments this into specific openings that define precise solder placement locations. This segmentation allows reliable attachment through optimized solder ball placement without requiring excessive overall device area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of increasing chip island area in two dimensions, the design uses the third dimension (vertical solder ball arrangement) to provide multiple solder connection points. This dimensional transition allows reliable attachment while maintaining a compact device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8097944B2Semiconductor device
Publication Date: 2012.01.17 INFINEON TECHNOLOGIES AG
  • US8097944B2 patent drawing
  • US8097944B2 patent drawing
  • US8097944B2 patent drawing

AI summary

A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity.