Semiconductor Chip Joining Strength via Metal Layer Width
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Solution Overview
Problem
Conventional methods for enhancing the joining strength between semiconductor chips through surface activation treatment can damage the pads and contaminate the joining apparatus, leading to reduced reliability.
Innovation Solution
A semiconductor device configuration that includes a first semiconductor chip with a first insulating layer and pads connected to a linear metal layer, and a second semiconductor chip with a second insulating layer and pads facing the first chip's pads, where the width of the metal layers is optimized based on the joining strength between the insulating layers and metal layers to improve bonding without activation treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If surface activation treatment is performed to improve joining strength between insulating layers, then joining strength is improved, but pads are damaged and copper flies about contaminating the apparatus
Solution Approach 1:
The invention divides the joining surface into distinct functional regions: pad regions for electrical connection and insulating layer regions for insulation. By segmenting the treatment approach, plasma treatment is applied selectively only to the insulating layer regions while pad regions are protected, preventing pad damage and copper contamination while still achieving improved joining strength in the insulating regions.
Solution Approach 2:
The invention applies different properties to different parts of the joining surface. The insulating layer regions receive plasma treatment to enhance their joining properties, while the pad regions maintain their original properties for optimal electrical connection. This local differentiation allows improvement of joining strength where needed without adversely affecting the pad regions.
2Reliability
If conventional joining methods are used without activation treatment, then pad damage and contamination are avoided, but joining strength between insulating layers is insufficient
Solution Approach 1:
The joining surface is segmented into pad regions and insulating layer regions, allowing selective plasma treatment of only the insulating regions. This segmentation enables the insulating layers to achieve sufficient joining strength for device reliability while the pad regions remain undamaged and free from contamination.
Solution Approach 2:
The invention uses a mask or protective structure as an intermediary element to control the plasma treatment process. This intermediary allows plasma to reach the insulating layer regions for activation while blocking the pad regions, thereby achieving both improved joining strength and prevention of pad damage simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the joining strength between semiconductor chips without the need for surface activation treatment, preventing pad damage and contamination, thereby improving the reliability of the semiconductor device.
Implementation Method 1
a system that activates the joining surface by plasma treatment to improve the joining strength
Data Source
AI summary
To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer. A width of the first metal layer and the second metal layer is a width based on a joining strength between the first insulating layer and the second insulating layer and a joining strength between the first metal layer and the second metal layer in an area from an end portion of the first semiconductor chip to the first pad.