Semiconductor Chip Package With Peripheral Contact Areas

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Solution Overview

Problem

Current semiconductor chip packages lack flexibility and modular applicability for efficient attachment to printed circuit boards and integration with additional devices, limiting their functionality and usability.

Innovation Solution

The semiconductor chip package design includes additional peripheral contact areas and external contact pins, with an encapsulation layer that can be filled with conductive materials, allowing for flexible connection options and integration of further devices, and can be fabricated as either surface-mounted or through-hole devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional semiconductor chip package design is used, then the structure is simple and manufacturing is easier, but the flexibility and modular applicability for attachment to boards and integration with additional devices is limited

Engineering Contradiction:
Improveflexibility and modular applicabilityVSAvoidpackage structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements multiple external contact elements (first, second, and third contact elements) that can serve different functions: the first contact elements connect to the semiconductor chip, the second contact elements provide board attachment options (both surface-mounted and through-hole configurations), and the third contact elements enable integration with additional devices. This multi-functional design allows a single package structure to fulfill multiple purposes, thereby improving adaptability and versatility without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The package structure is divided into distinct functional segments: the semiconductor chip, the encapsulation layer, multiple sets of contact elements (first, second, and third), and optional additional devices. This segmentation allows each component to be optimized independently and facilitates flexible configuration depending on the specific application requirements, enabling modular applicability while maintaining manageable overall complexity.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If additional contact elements and integration options are added, then the flexibility and functionality are improved, but the device complexity increases

Engineering Contradiction:
Improveconnection options and integration capabilityVSAvoidnumber of contact elements and structures
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple contact element types (first, second, and third contact elements) and additional devices within a single integrated package structure enclosed by the encapsulation layer. This merging approach consolidates what would otherwise be separate components into one unified device, improving versatility and connection options while containing the complexity within a single manufacturable unit rather than requiring multiple separate components.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9123708B2Semiconductor chip package
Publication Date: 2015.09.01 INFINEON TECH AUSTRIA AG
  • US9123708B2 patent drawing
  • US9123708B2 patent drawing
  • US9123708B2 patent drawing

AI summary

The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements.