Semiconductor Chip Package Structure for 3D Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional through silicon via technology faces challenges in stacking memory dies with different sizes and processes, as it requires a thinning process that can damage integrated circuits and is difficult to manage variations in die sizes.
Innovation Solution
A semiconductor chip package structure comprising a first and second semiconductor chip with exposed bonding surfaces and a supporting substrate, where the chips are electrically connected using wire units, allowing for easy stacking without the need for substrate thinning and accommodating different chip sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through silicon via technology is used to package memory chips in 3-dimensional structure, then packaging density and integration are improved, but substrate thinning process is required which damages integrated circuits and increases manufacturing difficulty
Solution Approach 1:
Instead of thinning the substrate first and then forming vias (traditional TSV approach), this patent inverts the sequence by forming conductor units through the full substrate thickness first, then thinning the substrate afterward. This ensures the integrated circuits remain protected during the via formation process, eliminating the risk of damage while achieving 3-dimensional packaging.
Solution Approach 2:
The conductor units are formed preliminarily through the entire substrate thickness before the substrate thinning process. This preliminary action allows the via holes and conductor units to be established when the substrate is still thick and robust, avoiding the fragility issues that would occur if thinning were performed first.
2Reliability
If traditional through silicon via method is used, then vertical electrical connection is achieved, but substrate thinning process is difficult and prone to damage integrated circuit
Solution Approach 1:
The patent reverses the conventional manufacturing sequence by forming the conductor units through the substrate first, then performing the thinning process. This inversion makes the manufacturing easier because the substrate is more robust during the via formation process, reducing the difficulty and risk associated with substrate handling.
Solution Approach 2:
The conductor units are formed in advance before substrate thinning. This preliminary formation of conductors allows the use of standard thick-substrate processing techniques, which are easier and more reliable, followed by a controlled thinning process that does not compromise the already-formed electrical connections.
3Adaptability or versatility
If memory dies with different sizes are to be stacked, then design flexibility is improved, but traditional through silicon via technology cannot accommodate different sizes
Solution Approach 1:
The supporting substrate is designed with a universal structure that can accommodate conductor units of various sizes and configurations. The substrate provides a common platform that supports memory dies of different dimensions, allowing the same basic packaging structure to be used for diverse chip sizes without requiring different manufacturing processes.
Solution Approach 2:
The conductor units are segmented and positioned at specific locations on the supporting substrate, allowing different-sized memory dies to be stacked at different positions. This segmentation enables flexible arrangement of chips with varying dimensions while maintaining proper electrical connections through the substrate.
Data Source
AI summary
A semiconductor chip package structure including a first semiconductor chip, a second semiconductor chip and a supporting substrate is provided. The first semiconductor chip includes at least a first conductor unit. The first conductor unit has a first bonding surface and a second bonding surface exposed from the first semiconductor chip. The second semiconductor chip includes at least a second conductor unit. The second conductor unit has a third bonding surface and a fourth bonding surface exposed from the second semiconductor chip. The third bonding surface is contacted with and electrically connected to the first bonding surface. The supporting substrate includes a wire unit for electrically connecting to at least one of the second bonding surface and the fourth bonding surface. A semiconductor chip and a semiconductor chip group are also provided.