Semiconductor Chip Pad Pitch and Resin Void Suppression
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Solution Overview
Problem
The challenge is to reduce the outer dimensions of semiconductor devices with multiple chips while avoiding voids formed during resin sealing, as existing methods using slits for alignment are inaccurate and limit the reduction of chip spacing.
Innovation Solution
A manufacturing method involving a lead frame with a die pad and notches for precise chip placement, where the distance between bonding pads is optimized to facilitate resin filling, ensuring efficient sealing without voids and allowing for smaller device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If slits are provided on the die pad for alignment, then chip placement accuracy is improved, but the distance between chips cannot be sufficiently reduced
Solution Approach 1:
The patent uses visual markers with distinct patterns (such as different shapes, sizes, or arrangements of notches/cutouts) on the die pad to enable optical alignment systems to distinguish between different chip placement areas. This eliminates the need for physical slits while maintaining alignment precision, allowing chips to be placed closer together.
2Length of stationary object
If the distance between chips is reduced to minimize device size, then outer dimensions are reduced, but voids form during resin sealing
Solution Approach 1:
The patent incorporates alignment markers and positioning features into the die pad structure before chip mounting. This preliminary arrangement of markers and notches ensures that chips are positioned with sufficient spacing for resin flow, preventing void formation while maintaining compact overall device dimensions.
3Device complexity
If multiple chips are mounted over one die pad, then device complexity is reduced, but alignment difficulty increases
Solution Approach 1:
The patent divides the single die pad into multiple distinct chip placement areas, each marked with unique visual markers (different notch patterns, positions, or configurations). This segmentation allows the alignment system to easily distinguish between different chip positions, simplifying the alignment process while enabling multiple chips to be mounted on one die pad.
Data Source
AI summary
A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.