Semiconductor Chip Panel Testing With Isolated Holder Contacts
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Solution Overview
Problem
There is a need for a practical and efficient method to test semiconductor chips and modules, particularly those with vertical transistor structures like IGBT transistors, to ensure they meet performance criteria before being delivered, as existing methods are inadequate for assessing their functionality and electrical characteristics.
Innovation Solution
A method and apparatus involving a semiconductor chip panel with embedded chips, a test contact device, and an electrically conducting holder are used to establish electrical contacts on both main faces of the chips, allowing for the measurement of functionality and electrical characteristics, with the test contact device and holder designed to facilitate contact and reduce particle interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a test method is designed to test multiple semiconductor chips simultaneously, then productivity increases, but it becomes difficult to ensure that only the intended chip is contacted, leading to measurement errors
Solution Approach 1:
The patent divides the testing process into individual chip-level operations. The holder is designed with multiple isolated contact regions, each corresponding to a specific chip position. The testing apparatus sequentially positions and tests each chip individually rather than attempting simultaneous multi-chip testing, ensuring measurement accuracy while maintaining reasonable productivity through systematic processing
Solution Approach 2:
The holder features locally optimized contact regions with specific geometric configurations (protrusions, recesses, contact pads) that are precisely positioned to match corresponding features on each chip. This local geometric matching ensures that only the intended chip makes contact with its designated test regions, preventing interference with adjacent chips while enabling efficient sequential testing
2Measurement precision
If the testing apparatus is designed to contact only one chip at a time, then measurement accuracy is ensured, but productivity decreases due to sequential testing
Solution Approach 1:
The holder is pre-configured with multiple contact regions and positioning features during manufacturing. Chips are pre-positioned on the holder in their correct orientations. The testing apparatus then performs rapid sequential testing by simply moving to the next pre-prepared position, eliminating the need for complex real-time alignment and reducing the overhead of individual chip handling
Solution Approach 2:
The holder acts as an intermediary device between the chips and the testing apparatus. It provides a stable, pre-configured platform that holds multiple chips in precise positions and facilitates their individual contact with test probes. This intermediary structure enables efficient sequential testing by managing chip positioning and contact establishment, thereby improving productivity without compromising measurement accuracy
3Reliability
If particles are present on the chip surface during testing, then contamination occurs affecting reliability, but adding particle removal steps increases process complexity
Solution Approach 1:
The testing method explicitly removes particles as a separate preliminary step before electrical testing. The holder design includes features that facilitate particle removal (such as specific contact surface geometries and positioning structures). By extracting the particle removal function as a distinct preparatory step and integrating it into the holder design, the main testing apparatus remains relatively simple while still achieving reliable particle-free testing
Solution Approach 2:
Particle removal is performed as a preliminary action before the actual electrical testing begins. The holder and testing process are designed to ensure chips are free of particles prior to contact with test probes. This preliminary cleaning step, built into the process flow and holder design, prevents contamination during testing without requiring complex real-time particle management during the measurement itself
Data Source
AI summary
A semiconductor chip panel includes a plurality of semiconductor chips embedded in an encapsulation material. At least part of the semiconductor chips comprise a first electrical contact element on a first main face and a second electrical contact element on a second main opposite to the first main face, respectively. One of the plurality of semiconductor chips is tested by establishing an electrical contact between a test contact device and the first electrical contact element and between an electrically conductive holder and the second contact element.